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Commit Graph

183529 Commits

Author SHA1 Message Date
Sander de Smalen
e877a2fb7c Relanding r368987 [AArch64] Change location of frame-record within callee-save area.
Changes:
There was a condition for `!NeedsFrameRecord` missing in the assert. The
assert in question has changed to:

+    assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP ||
+            RPI.Reg1 == AArch64::LR) &&
+           "FrameRecord must be allocated together with LR");

This addresses PR43016.

llvm-svn: 369122
2019-08-16 15:42:28 +00:00
Evandro Menezes
6cab74d622 [InstCombine] Simplify pow(2.0, itofp(y)) to ldexp(1.0, y)
Simplify `pow(2.0, itofp(y))` to `ldexp(1.0, y)`.

Differential revision: https://reviews.llvm.org/D65979

llvm-svn: 369120
2019-08-16 15:33:41 +00:00
Cyndy Ishida
a60baad757 [TextAPI] Update reader to be supported by lib/Object
Summary:
To be able to use the TextAPI/Reader for tbd file consumption (by libObject)
it gets passed a MemoryBufferRef which isn't castable to MemoryBuffer.
Updated the tests to expect that input as well.

Reviewers: ributzka, steven_wu

Reviewed By: steven_wu

Subscribers: hiraditya, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66147

llvm-svn: 369119
2019-08-16 15:30:48 +00:00
David Green
4dcd0a1359 [ARM] MVE sext of a load is free
MVE also has some sext of loads, which will be free just as scalar
instructions are.

Differential Revision: https://reviews.llvm.org/D66008

llvm-svn: 369118
2019-08-16 15:13:37 +00:00
Roman Lebedev
6c3205dea8 [InstCombine] Shift amount reassociation in bittest: trunc-of-shl (PR42399)
Summary:
This is continuation of D63829 / https://bugs.llvm.org/show_bug.cgi?id=42399

I thought naive pattern would solve my issue, but nope, it involved truncation,
thus more folds needed.. This isn't really the fold i'm interested in,
i need trunc-of-lshr, but i'we decided to start with `shl` because it's simpler.

In this case, no extra legality checks are needed:
https://rise4fun.com/Alive/CAb

We should be careful about not increasing instruction count,
since we need to produce `zext` because `and` is done in wider type.

Reviewers: spatel, nikic, xbolva00

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66057

llvm-svn: 369117
2019-08-16 15:10:41 +00:00
Simon Pilgrim
5e41900f3c [X86][SSE] Add shuffled load tests from PR16739
llvm-svn: 369116
2019-08-16 14:47:59 +00:00
Simon Pilgrim
151c6a70ee Revert rL369112 : [X86][SSE] Add shuffled load tests from PR16739
I left typos in this from a WIP copy - reverting and I'll recommit.

llvm-svn: 369115
2019-08-16 14:31:45 +00:00
Luis Marques
440445b5a4 [RISCV] Convert registers from unsigned to Register
Only in public interfaces that have not yet been converted should there remain
registers with unsigned type.

Differential Revision: https://reviews.llvm.org/D66252

llvm-svn: 369114
2019-08-16 14:27:50 +00:00
Simon Pilgrim
b287619349 [X86][SSE] Add shuffled load tests from PR16739
llvm-svn: 369112
2019-08-16 14:26:11 +00:00
Paul Walker
812a84f6cc [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions.
Summary:
AArch64InstrInfo::getInstSizeInBytes is incorrectly treating meta
instructions (e.g. CFI_INSTRUCTION) as normal instructions and
giving them a size of 4.

This results in branch relaxation calculating block sizes wrong.
Branch relaxation also considers alignment and thus a single
mistake can result in later blocks being incorrectly sized even
when they themselves do not contain meta instructions.

The net result is we might not relax a branch whose destination is
not within range.

Reviewers: nickdesaulniers, peter.smith

Reviewed By: peter.smith

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66337

llvm-svn: 369111
2019-08-16 14:17:52 +00:00
Simon Pilgrim
69d84d7cd7 [X86] Remove unused include. NFCI.
We don't use anything from TargetOptions.h directly and its included via TargetLowering.h anyhow.

llvm-svn: 369110
2019-08-16 14:05:46 +00:00
David Green
ef6873f702 [ARM] Correct register for narrowing and widening MVE loads and stores.
The widening and narrowing MVE instructions like VLDRH.32 are only permitted to
use low tGPR registers. This means that if they are used for a stack slot,
where the register used is only decided during frame setup, we need to be able
to correctly pick a thumb1 register over a normal GPR.

This attempts to add the required logic into eliminateFrameIndex and
rewriteT2FrameIndex, only picking the FrameReg if it is a valid register for
the operands register class, and picking a valid scratch register for the
register class.

Differential Revision: https://reviews.llvm.org/D66285

llvm-svn: 369108
2019-08-16 13:42:39 +00:00
Sanjay Patel
60f581d78d [x86] fix fdiv test; NFC
The test was just added with rL369106, but forgot to update the instruction
along with the test name.

llvm-svn: 369107
2019-08-16 13:31:23 +00:00
Sanjay Patel
479bcc1e8a [x86] add tests for fdiv with variable operands; NFC
D66050 proposes to change the estimate sequence, but we
don't seem to have test coverage for the common case.

llvm-svn: 369106
2019-08-16 13:23:52 +00:00
Florian Hahn
8f1e449ac9 Revert [CodeGen] Do the Simple Early Return in block-placement pass to optimize the blocks
This reverts r368997 (git commit 2a903c0b679bae1919f9fc01f78e4bc6cff2add0)

It looks like this commit adds invalid predecessors to MBBs. The example
below fails the verifier after MachineBlockPlacement (run llc
-verify-machineinstrs):

@global.4 = external constant i8*

declare i32 @zot(...)

define i16* @snork.67() personality i8* bitcast (i32 (...)* @zot to i8*) {
bb:
  invoke void undef()
          to label %bb5 unwind label %bb4

bb4:                                              ; preds = %bb
  %tmp = landingpad { i8*, i32 }
          catch i8* null
  unreachable

bb5:                                              ; preds = %bb
  %tmp6 = load i32, i32* null, align 4
  %tmp7 = icmp eq i32 %tmp6, 0
  br i1 %tmp7, label %bb14, label %bb8

bb8:                                              ; preds = %bb11, %bb5
  invoke void undef()
          to label %bb9 unwind label %bb11

bb9:                                              ; preds = %bb8
  %tmp10 = invoke i16* undef()
          to label %bb14 unwind label %bb11

bb11:                                             ; preds = %bb9, %bb8
  %tmp12 = landingpad { i8*, i32 }
          cleanup
          catch i8* bitcast (i8** @global.4 to i8*)
  %tmp13 = icmp ult i64 undef, undef
  br i1 %tmp13, label %bb8, label %bb14

bb14:                                             ; preds = %bb11, %bb9, %bb5
  %tmp15 = phi i16* [ null, %bb5 ], [ null, %bb11 ], [ %tmp10, %bb9 ]
  ret i16* %tmp15
}

llvm-svn: 369104
2019-08-16 13:19:29 +00:00
Bjorn Pettersson
0c9ab6e44f [DAGCombiner] Add simple folds for SMULFIX/UMULFIX/SMULFIXSAT
Summary:
Add the following DAGCombiner folds for mulfix being
one of SMULFIX/UMULFIX/SMULFIXSAT:
  (mulfix x, undef, scale) -> 0
  (mulfix x, 0, scale) -> 0

Also added canonicalization of constants to RHS.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66052

llvm-svn: 369103
2019-08-16 13:16:48 +00:00
Bjorn Pettersson
9d4e6430d2 [X86] Add test case for future MULFIX DAG combine folds. NFC
Add some test cases displaying the lack of DAG combine
folds for SMULFIX/UMULFIX/SMULFIXSAT when either
multiplicand is undef or zero.

It seems like widening vector legalization for X86 can
introduce fixed point multiplication of undef values.
So that is one way that such operations could appear
during ISel.

Multiplication with zero is probably more unlikely, and
could potentially be handled by InstCombine. But I do
not think it would hurt to do such folds in DAGCombiner.

This patch only adds the test case. The folds will be
added in a follow up patch.

llvm-svn: 369102
2019-08-16 13:16:38 +00:00
David Green
c40c592399 [ARM] Don't pretend we know how to generate MVE VLDn
We don't yet know how to generate these instructions for MVE. And in the case
of VLD3, we don't even have the instruction. For the moment don't tell the
vectoriser that we have VLD4, just to end up serialising the results.

Differential Revision: https://reviews.llvm.org/D66009

llvm-svn: 369101
2019-08-16 13:06:49 +00:00
Lewis Revill
47463e82c7 [RISCV] Allow parsing of bare symbols with offsets
This patch allows symbols followed by an expression for an offset to be
parsed as bare symbols.

Differential Revision: https://reviews.llvm.org/D57332

llvm-svn: 369097
2019-08-16 12:00:56 +00:00
Benjamin Kramer
8b30fad250 Revert "[CallGraph] Refine call graph for indirect calls with !callees metadata"
This reverts commit r369025. Crashes clang, test case is on the mailing
list.

llvm-svn: 369096
2019-08-16 10:59:18 +00:00
Lewis Revill
2fe2bb2271 [RISCV] Lower inline asm constraint A for RISC-V
This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296

llvm-svn: 369095
2019-08-16 10:28:34 +00:00
Simon Pilgrim
8062e3ba80 [SLPVectorizer] Silence null dereference warning. NFCI.
cppcheck + MSVC analyzer both over zealously warn that we might dereference a null Bundle pointer - add an assertion to check for null to silence the warning, plus its a good idea to check that we succeeded in finding a schedule bundle anyway....

llvm-svn: 369094
2019-08-16 10:28:23 +00:00
Jeremy Morse
4e5da422ab [DebugInfo] Handle complex expressions with spills in LiveDebugValues
In r369026 we disabled spill-recognition in LiveDebugValues for anything
that has a complex expression. This is because it's hard to recover the
complex expression once the spill location is baked into it.

This patch re-enables spill-recognition and slightly adjusts the DBG_VALUE
insts that LiveDebugValues tracks: instead of tracking the last DBG_VALUE
for a variable, it tracks the last _unspilt_ DBG_VALUE. The spill-restore
code is then able to access and copy the original complex expression; but
the rest of LiveDebugValues has to be aware of the slight semantic shift,
and produce a new spilt location if a spilt location is propagated between
blocks.

The test added produces an incorrect variable location (see FIXME), which
will be the subject of future work.

Differential Revision: https://reviews.llvm.org/D65368

llvm-svn: 369092
2019-08-16 10:04:17 +00:00
Tim Northover
fbd80b377d AssumptionCache: remove old affected values after RAUW.
If they're left in the cache then they can't be removed efficiently when the
cache is notified to unlink a @llvm.assume call, and that can lead to values
from different functions entirely remaining there.

llvm-svn: 369091
2019-08-16 09:34:27 +00:00
Florian Hahn
6ecdafe314 [ValueTracking] Fix recurrence detection to check both PHI operands.
Summary:
Currently we fail to compute known bits for recurrences where the
first incoming value is the start value of the recurrence.

Instead of exiting the loop when the first incoming value is not
the step of the recurrence, continue to check the second incoming
value.

The original code uses a loop to handle both cases, but incorrectly
exits instead of continuing.

Reviewers: lebedev.ri, spatel, nikic

Reviewed By: lebedev.ri

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66216

llvm-svn: 369088
2019-08-16 09:15:02 +00:00
Craig Topper
41b64b38c5 [X86] Manually reimplement getTargetInsertSubreg in X86DAGToDAGISel::matchBitExtract so we can call insertDAGNode on the target constant.
This is needed to maintain the topological sort order.

Fixes PR42992.

llvm-svn: 369084
2019-08-16 04:47:44 +00:00
Igor Kudrin
677bb1f63a Remove the temporary code. NFC.
That should have been done in rL368156 but somehow was missed.

llvm-svn: 369082
2019-08-16 03:40:04 +00:00
Nico Weber
8e559d6c8a Revert r368987, it caused PR43016.
llvm-svn: 369080
2019-08-16 02:21:21 +00:00
Chen Zheng
a870fcab46 [PowerPC] add testcases for folding frame offset - NFC
llvm-svn: 369077
2019-08-16 01:52:50 +00:00
Nico Weber
4475276f7e gn build: Merge r369064
llvm-svn: 369074
2019-08-16 00:04:48 +00:00
Nico Weber
3ada940abc gn build: Merge r369061
llvm-svn: 369073
2019-08-16 00:04:42 +00:00
Jonas Devlieghere
15dd7d938d [DebugLine] Don't try to guess the path style
In r368879 I made an attempt to guess the path style from the files in
the line table. After some consideration I now think this is a poor
idea. This patch undoes that behavior and instead adds an optional
argument to specify the path style. This allows us to make that decision
elsewhere where we have more information. In case of LLDB based on the
Unit.

llvm-svn: 369072
2019-08-15 23:53:15 +00:00
Volkan Keles
e1dc48d1b9 [GlobalISel] CSEMIRBuilder: Add support for G_GEP
Summary:
This patch adds G_GEP to `shouldCSEOpc` so that it can be CSEd. It also refactors
`translateGetElementPtr` by replacing `createGenericVirtualRegister` calls with types.

Reviewers: aditya_nandakumar, arsenm, dsanders, paquette, aemerson

Reviewed By: aditya_nandakumar

Subscribers: wdng, rovka, javed.absar, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66316

llvm-svn: 369070
2019-08-15 23:45:45 +00:00
Eli Friedman
db6f309e58 [ARM][LowOverheadLoops] Fix generated code for "revert".
Two issues:

1. t2CMPri shouldn't use CPSR if it isn't predicated. This doesn't
really have any visible effect at the moment, but it might matter in the
future.
2. The t2CMPri generated for t2WhileLoopStart might need to use a
register that isn't LR.

My team found this because we have a patch to track register liveness
late in the pass pipeline. I'll look into upstreaming it to help catch
issues like this earlier.

Differential Revision: https://reviews.llvm.org/D66243

llvm-svn: 369069
2019-08-15 23:35:53 +00:00
David L. Jones
96783c0442 [NewPM][PassInstrumentation] Fix test added in r369024.
llvm-lto2 doesn't treat "-" as stdout, so the test added in r369024 creates a
file named "-.0". This patch makes the test look more like other tests that use
llvm-lto2.

llvm-svn: 369066
2019-08-15 23:24:14 +00:00
Jonas Devlieghere
50ee2200f6 [Support] Re-introduce the RWMutexImpl for macOS < 10.12
In r369018, Benjamin replaced the custom RWMutex implementation with
their C++14 counterpart. Unfortunately, std::shared_timed_mutex is only
available on macOS 10.12 and later. This prevents LLVM from compiling
even on newer versions of the OS when you have an older deployment
target. This patch reintroduced the old RWMutexImpl but guards it by the
macOS availability macro.

Differential revision: https://reviews.llvm.org/D66313

llvm-svn: 369064
2019-08-15 23:07:20 +00:00
Evgeniy Stepanov
1f95a6ee94 Move isPointerOffset function to ValueTracking (NFC).
Summary: To be reused in MemTag sanitizer.

Reviewers: pcc, vitalybuka, ostannard

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66165

llvm-svn: 369062
2019-08-15 22:58:28 +00:00
Diego Trevino Ferrer
fab54799c5 [Bugpoint redesign] Added Pass to Remove Global Variables
Summary:
This pass tries to remove Global Variables, as well as their derived uses. For example if a variable `@x` is used by `%call1` and `%call2`, both these uses and the definition of `@x` are deleted. Moreover if `%call1` or `%call2` are used elsewhere those uses are also deleted, and so on recursively.

I'm still uncertain if this pass should remove derived uses, I'm open to suggestions.

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64176

> llvm-svn: 368918

llvm-svn: 369061
2019-08-15 22:54:09 +00:00
Diego Trevino Ferrer
f3ddd9e99c [Bugpoint redesign] Output option can now print to STDOUT
Summary:
This also changes all the outs() statements to errs() so the output and
progress streams don't get mixed.

This has been added because D64176 had flaky tests, which I believe were because the reduced file was being catted into `FileCheck`, instead of being pass from STDOUT directly.

Reviewers: chandlerc, dblaikie, xbolva00

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66314

llvm-svn: 369060
2019-08-15 22:39:43 +00:00
Jonas Devlieghere
f6311a140d Revert "[Support] Re-introduce the RWMutexImpl for macOS < 10.12"
This doesn't work (yet).

llvm-svn: 369059
2019-08-15 22:24:21 +00:00
Hubert Tong
e56a69ac7c [AIX] For XL, pick GCC-compatible std & default warning options
Summary:
LLVM now requires C++14. For IBM XL compilers with C++14 support, this
can be done with the GCC-style options. The relevant block in the CMake
file is split up into smaller parts as part of this patch to allow the
common cases to be shared.

Reviewers: jfb, jasonliu, daltenty, xingxue

Reviewed By: jfb, xingxue

Subscribers: mstorsjo, mgorny, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66256

llvm-svn: 369058
2019-08-15 22:23:53 +00:00
Philip Reames
3fe9376581 [SDAG] Minor code cleanup/standardization of atomic accessors [NFC]
llvm-svn: 369057
2019-08-15 22:21:14 +00:00
Jonas Devlieghere
8b036293ff [Support] Re-introduce the RWMutexImpl for macOS < 10.12
In r369018, Benjamin replaced the custom RWMutex implementation with
their C++14 counterpart. Unfortunately, std::shared_timed_mutex is only
available on macOS 10.12 and later. This prevents LLVM from compiling
even on newer versions of the OS when you have an older deployment
target. This patch reintroduced the old RWMutexImpl but guards it by the
macOS availability macro.

Differential revision: https://reviews.llvm.org/rL369018

llvm-svn: 369056
2019-08-15 22:19:38 +00:00
Jinsong Ji
1bcb6d2dd5 [Utils][NFC] Copy bisect usage documents from commit msg into script.
Copy the message into script, so that new users won't need to dig into
commit messages to figure out how to use.

The message are copied directly from Michael's commit message in
https://reviews.llvm.org/rL214610.

llvm-svn: 369054
2019-08-15 22:07:59 +00:00
Evgeniy Stepanov
ce5f1f9209 Add missing MIR serialization text for AArch64II::MO_TAGGED.
Reviewers: pcc

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66312

llvm-svn: 369053
2019-08-15 22:03:55 +00:00
Alina Sbirlea
e7ba05415f [MemorySSA] Remove restrictive asserts.
The verification I added has overly restrictive asserts.
Unreachable blocks can have any incoming value in practice, after an
update due to a "replaceAllUses" call when the repalced entry is
LiveOnEntry.

llvm-svn: 369050
2019-08-15 21:20:08 +00:00
Nico Weber
693ececc82 gn build: Merge r369039
llvm-svn: 369047
2019-08-15 21:00:33 +00:00
Nico Weber
0562fc402f gn build: Merge r369018
llvm-svn: 369046
2019-08-15 21:00:26 +00:00
JF Bastien
3fcfd786dd Fix nm on GCC 5.1 after the C++14 move
Summary:
As in D66306, fix the invocation of std::sort with std::function by not using
std::function, since it's easier to read and is broken in libstdc++ from GCC 5.1
(see https://gcc.gnu.org/PR65942).

Reviewers: thakis

Subscribers: jkorous, mgrang, dexonsmith, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66310

llvm-svn: 369045
2019-08-15 20:38:42 +00:00
Daniel Sanders
f8a414589e Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&

Depends on D65919

Reviewers: arsenm, bogner, craig.topper, RKSimon

Reviewed By: arsenm

Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65962

llvm-svn: 369041
2019-08-15 19:22:08 +00:00