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Commit Graph

766 Commits

Author SHA1 Message Date
Daniel Sanders
754a2807ef [mips][ias] R_MIPS_GOT_(PAGE|OFST) do not need symbols
Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: https://reviews.llvm.org/D22458

llvm-svn: 275968
2016-07-19 10:58:06 +00:00
Daniel Sanders
57cec27c07 [mips] Correct label prefixes for N32 and N64.
Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).

This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D22412

llvm-svn: 275967
2016-07-19 10:49:03 +00:00
Zlatko Buljan
25db5cab21 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
2016-07-11 07:41:56 +00:00
Hrvoje Varga
52c95ef5b8 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850
2016-06-27 08:23:28 +00:00
Daniel Sanders
b188a9dbc3 [mips] Use --check-prefixes where appropriate. NFC.
llvm-svn: 273669
2016-06-24 12:23:17 +00:00
Daniel Sanders
14a7ad6b92 [mips] Don't derive the default ABI from the CPU in the backend.
Summary:
The backend has no reason to behave like a driver and should generally do
as it's told (and error out if it can't) instead of trying to figure out
what the API user meant. The default ABI is still derived from the arch
component as a concession to backwards compatibility.

API-users that previously passed an explicit CPU and a triple that was
inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a
different ABI to what they got before. However, it's expected that there
are no such users on the basis that CodeGen has been asserting that the
triple is consistent with the selected ABI for several releases. API-users
that were consistent or passed '' or 'generic' as the CPU will see no
difference.

Reviewers: sdardis, rafael

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21466

llvm-svn: 273557
2016-06-23 12:42:53 +00:00
Daniel Sanders
2790c5281d [mips][ias] Integers are not registers.
Summary:
When parseAnyRegister() encounters a symbol alias, it parses integers and adds
a corresponding expression to the operand list. This is clearly wrong since the
only operands that parseAnyRegister() should be accepting are registers.

It's not clear why this code was added and there are no test cases that cover
it. I think it might be leftover from when searchSymbolAlias() was more widely
used.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21377

llvm-svn: 273555
2016-06-23 10:54:09 +00:00
Simon Dardis
d382333dbe [mips] Fix dext/dins definitions
dext and dins, along with their 'm' and 'u' variants are defined in mips64r2,
not mips64.

Reviewers: dsanders, vkalintiris

Differential Review: http://reviews.llvm.org/D21608

llvm-svn: 273549
2016-06-23 09:06:20 +00:00
Daniel Sanders
aed2e151eb [llvm-objdump] Support detection of feature bits from the object and implement this for Mips.
Summary:
The Mips implementation only covers the feature bits described by the ELF
e_flags so far. Mips stores additional feature bits such as MSA in the
.MIPS.abiflags section.

Also fixed a small bug this revealed where microMIPS wouldn't add the
EF_MIPS_MICROMIPS flag when using -filetype=obj.

Reviewers: echristo, rafael

Subscribers: rafael, mehdi_amini, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21125

llvm-svn: 272880
2016-06-16 09:17:03 +00:00
Hrvoje Varga
ffeed40324 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions
Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876
2016-06-16 07:06:25 +00:00
Zlatko Buljan
5cbd78beb4 [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions
Differential Revision: http://reviews.llvm.org/D16719

llvm-svn: 272764
2016-06-15 07:46:24 +00:00
Daniel Sanders
234846b9fd [mips][ias] Implement one N32 case (of two) for .cpsetup.
This patch implements the N32 case where -mno-shared is in effect. The case
where -mshared is in effect will be added later since doing that now requires
additional changes to how we handle %hi(%neg(%gp_rel(foo))) expressions to
emit the three relocations as three relocations (currently only one of the
three would be emitted) which then requires further changes to our MCFixup
handling.

While we could fix both cases together, fixing the -mno-shared case allows us
to fix the ELFCLASS bug (where N32 incorrectly uses ELFCLASS64 instead of
ELFCLASS32) in a way that allows cpsetup.s to check for a correct output instead
of another incorrect output.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D21131

llvm-svn: 272652
2016-06-14 10:13:47 +00:00
Hrvoje Varga
62d5d2ff36 [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions
Differential Revision: http://reviews.llvm.org/D11798

llvm-svn: 272259
2016-06-09 12:57:23 +00:00
Daniel Sanders
70d63fbd2e [mips] Remove CPU-only triples from llvm-objdump commands.
Summary: They aren't necessary since llvm-objdump can auto-detect the architecture.

Reviewers: sdardis

Subscribers: jfb, dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20904

llvm-svn: 271653
2016-06-03 10:22:22 +00:00
Daniel Sanders
1a3a82d3cc [mips] Implement 'la' macro in PIC mode for O32.
Summary:
N32 support will follow in a later patch since the symbol version of 'la'
incorrectly believes N32 to have 64-bit pointers and rejects it early.

This fixes the three incorrectly expanded 'la' macros found in bionic.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20820

llvm-svn: 271644
2016-06-03 09:53:06 +00:00
Simon Dardis
8d2c8c8209 [mips] Remove tests which should have been deleted.
The two xfail tests for mis32r6 & mips64r6 were supposed
to be removed in r271301.

llvm-svn: 271306
2016-05-31 17:52:29 +00:00
Simon Dardis
fb52d15569 [mips] Enforce compact branch register restrictions
Enforce compact branch register restrictions such as the use of the zero
register, both operands being the same register. Emit clear error in such
cases as the issue is subtle.

For bovc and bnvc, silently fixup such cases when emitting objects directly,
like LLVM started doing in rL269899.

Reviewers: vkalintiris, dsanders

Differential Review: http://reviews.llvm.org/D20475

llvm-svn: 271301
2016-05-31 17:34:42 +00:00
Simon Dardis
18b7d75488 [mips] Weaken asm predicate for memory offsets
The isMemWithSimmOffset predicate rejects relocations which is incorrect
behaviour. Linkers and other tools should handle|warn|error when the
field overflows.

Reviewers: dsanders, vkalintiris

Differential Revision: http://reviews.llvm.org/D20727

llvm-svn: 270995
2016-05-27 13:56:36 +00:00
Zoran Jovanovic
07314a2bff ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation
Differential Revision: http://reviews.llvm.org/D15526

llvm-svn: 270048
2016-05-19 12:20:40 +00:00
Zlatko Buljan
3d28e4b8d5 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
2016-05-19 07:31:28 +00:00
Rafael Espindola
6da3617e7f Don't pass a Reloc::Model to MC.
MC only needs to know if the output is PIC or not. It never has to
decide about creating GOTs and PLTs for example. The only thing that
MC itself uses this information for is expanding "macros" in sparc and
mips. The rest I am pretty sure could be moved to CodeGen.

This is a cleanup and isolates the code from future changes to
Reloc::Model.

llvm-svn: 269909
2016-05-18 11:58:50 +00:00
Zlatko Buljan
af377b7a57 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D15418

llvm-svn: 269883
2016-05-18 06:54:59 +00:00
Rafael Espindola
71b6b2942e Don't pass relocation-model= to tests that don't need it.
Very few things in MC itself use the option. Most of the code that that
uses it could be move to CodeGen.

llvm-svn: 269871
2016-05-18 00:27:17 +00:00
Zoran Jovanovic
c3850b81b8 [mips][microMIPS] Implement BEQZC and BNEZC instructions
Differential Revision: http://reviews.llvm.org/D15417

llvm-svn: 269755
2016-05-17 11:10:15 +00:00
Zlatko Buljan
0fef23e430 [mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions
Differential Revision: http://reviews.llvm.org/D16182

llvm-svn: 269752
2016-05-17 09:32:58 +00:00
Daniel Sanders
7ac931ce16 [mips][ias] Fix R_MICROMIPS_GOT16 evaluation and eliminate symbol for R_MICROMIPS_(GOT|HI|LO)16
Summary:
The failure r269410 worked around turned out to be caused by an incorrect
evaluation of R_MICROMIPS_GOT16 which then caused the GOT entries to be
incorrect.

This patch fixes the evaluation and reverts r269410.

Reviewers: sdardis, vkalintiris, rafael

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20242

llvm-svn: 269641
2016-05-16 09:33:59 +00:00
Daniel Sanders
0ed85c1ebe [mips][ias] EF_MIPS_MICROMIPS should iff microMIPS code was emitted.
Summary:
This fixes PR27682. Additionally, '.set micromips' by itself is not sufficient
to raise the EF_MIPS_MICROMIPS flag. It is also necessary to emit a microMIPS
instruction. This has also been fixed.

Reviewers: sdardis, vkalintiris, rafael

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20214

llvm-svn: 269639
2016-05-16 09:10:13 +00:00
Zoran Jovanovic
e9d6f29fb1 [mips] Addition of a third operand to the instructions [d]div, [d]divu
Author: obucina
Reviewers: dsanders
Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register
Differential Revision: http://reviews.llvm.org/D16888

llvm-svn: 269636
2016-05-16 08:57:59 +00:00
Daniel Sanders
80eaa377a6 [mips][ias] Work around yet another incorrect microMIPS relocation evaluation exposed by r268900.
It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated
incorrectly in a small number of the LNT tests at this point. However, it's not
related to the STO_MIPS_MICROMIPS issue.

At this point all the microMIPS-related changes of r268900 have been reverted.

llvm-svn: 269410
2016-05-13 12:07:14 +00:00
Hrvoje Varga
9dc958973e [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions
Differential Revision: http://reviews.llvm.org/D14117

llvm-svn: 269408
2016-05-13 11:32:53 +00:00
Daniel Sanders
723ca9cb5e [mips][ias] Fix O32 .cprestore directive when inside .set noat region and offset is in range.
Summary:
This expands on r269179 to fix an additional case that was not covered by our
tests. The assembler temporary is not needed when the .cprestore offset fits
inside a simm16 and it is not an error to use it inside a '.set noat' in this
case.

Reviewers: emaste, seanbruno, sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20199

llvm-svn: 269295
2016-05-12 14:01:50 +00:00
Daniel Sanders
ace879545c [mips][ias] Work around incorrect another microMIPS relocation evaluation exposed by r268900
As explained in r269196, microMIPS has a special case that is not correctly
implemented in LLVM. If we have a symbol 'foo' which is equivalent to
'.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is
'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11.

This commit reverts a little more of the effect of r268900 by keeping the
symbol when the STO_MIPS_MICROMIPS flag is set for R_MIPS_GPREL32 relocations.
This fixes SingleSource/UnitTests/2003-08-11-VaListArg, and
SingleSource/UnitTests/2003-05-07-VarArgs for microMIPS.

I believe there are additional relocations that have the same issue (e.g.
R_MIPS_64, and R_MIPS_GPREL16) but for now I'm focusing on restoring our
internal buildbots back to the green state we had in r268899.

llvm-svn: 269294
2016-05-12 13:39:13 +00:00
Hrvoje Varga
c4cdcea6eb Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"
This reverts commit r269176 as it caused test-suite failure.

llvm-svn: 269287
2016-05-12 12:46:06 +00:00
Daniel Sanders
202cd56665 [mips][ias] Correct ELF eflags when Octeon is the target.
Reviewers: sdardis

Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D18899

llvm-svn: 269283
2016-05-12 11:31:19 +00:00
Daniel Sanders
f64c0bb52e [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in needsRelocateWithSymbol()
Summary:
This eliminates the default case for N64 that was left out of r269047.

The change to R_MIPS_SUB is needed in this patch to make this testable since
%lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get
a compound relocation from the assembler.

Reviewers: sdardis, rafael

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20097

llvm-svn: 269280
2016-05-12 10:55:00 +00:00
Daniel Sanders
b13f3435de [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by r268900
microMIPS has a special case that is not correctly implemented in LLVM. If we
have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an
R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The
in-place addend should therefore be 0x11.

Work around this by partially reverting the effect of r268900 by keeping the
symbol when the STO_MIPS_MICROMIPS flag is set. This fixes
SingleSource/Regression/C/PR640 for microMIPS.

llvm-svn: 269196
2016-05-11 15:44:23 +00:00
Daniel Sanders
3b97b8630a [mips][ias] Fix N32 and N64 .cprestore directive when inside .set noat region.
Summary:
r268058 unintentionally made the retrieval of the current assembler temporary
unconditional. This was fine for the existing tests but it broke the cases
where the assembler temporary is not needed (N32/N64 or not PIC) and is
unavailable due to a '.set noat' directive.

This fixes FreeBSD's libc.

Reviewers: emaste, sdardis, seanbruno

Subscribers: dsanders, emaste, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20093

llvm-svn: 269179
2016-05-11 12:48:19 +00:00
Hrvoje Varga
393783b540 [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D19713

llvm-svn: 269176
2016-05-11 12:12:24 +00:00
Hrvoje Varga
a728453644 [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions
Differential Revision: http://reviews.llvm.org/D16800

llvm-svn: 269169
2016-05-11 11:17:04 +00:00
Daniel Sanders
0c5254b797 [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() (except for N64).
Following post-commit comments on r268900 from Rafael Espindola:
The missing relocations are now explicitly listed in the switch statement with
appropriate FIXME comments and the default path is now unreachable. The
temporary exception to this is that compound relocations for N64 still have a
default path that returns true. This is because fixing that case ought to be a
separate patch.

Also make R_MIPS_NONE return false since it has no effect on the section data.

llvm-svn: 269047
2016-05-10 12:17:04 +00:00
Daniel Sanders
828a69bd74 [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.
Summary:
In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16
make the same decision on both relocs in the reloc pair but in practice
this isn't as hard as it sounds and only limits the complexity of the
predicate used. We handle all three with the same code to ensure their
decisions always agree with each other.

Reviewers: sdardis

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19016

llvm-svn: 268900
2016-05-09 10:21:14 +00:00
Zlatko Buljan
4c55849feb [mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
2016-05-09 08:07:28 +00:00
Daniel Sanders
9b9d5f9f6f [mips] Fix inconsistent .cprestore behaviour between direct object emission and assembling.
Summary:
Direct object emission has an initialization order problem where an
InitMCObjectFile is called after MipsTargetELFStreamer determines whether
PIC is enabled by default or not. There doesn't seem to be point that
initializes all cases so split the responsibility between
MipsTargetELFStreamer and MipsAsmPrinter.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19728

llvm-svn: 268737
2016-05-06 14:37:24 +00:00
Daniel Sanders
cd4dc5cad8 [mips] Correct the ordering of HI/LO pairs in the relocation table.
Summary:
There seems to have been a misunderstanding as to the meaning of 'offset' in
the rules laid down by our ABI. The previous code believed that 'offset' meant
the offset within the section that the relocation is applied to. However, it
should have meant the offset from the symbol used in the relocation expression.

This patch adds two fields to ELFRelocationEntry and uses them to correct the
order of relocations for MIPS. These fields contain:
* The original symbol before shouldRelocateWithSymbol() is considered. This
  ensures that R_MIPS_GOT16 is able to correctly distinguish between local and
  external symbols, allowing us to tell whether %got() requires a matching
  %lo() or not (local symbols require one, external symbols don't). It also
  prevents confusing cases where the fuzzy matching rules cause things like
  %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s.
* The original offset before shouldRelocateWithSymbol() is considered. The
  existing Addend field is always zero when the object uses in place addends
  (because it's already moved it to the encoding) but MIPS needs to use the
  original offset to ensure that the linker correctly calculates the carry-in
  bit for %hi() and %got().

IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of
the table to ensure that the linker rejects the table (we're unable to report
such errors directly). The alternatives to this risk accidental matching
against inappropriate relocations which may silently compute incorrect values
due to an incorrect carry bit between the %lo() and %hi()/%got().

Reviewers: sdardis

Subscribers: dsanders, sdardis, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D19718

llvm-svn: 268733
2016-05-06 13:49:25 +00:00
Zlatko Buljan
a375151a77 [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions
Differential Revision: http://reviews.llvm.org/D15744

llvm-svn: 268714
2016-05-06 08:24:14 +00:00
Nirav Dave
ed0981bcb7 Fix Mips Parser error reporting
[mips] On error, ParseDirective should always return false to signify that the
directive was understood.

Reviewers: dsanders, vkalintiris, sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19929

llvm-svn: 268630
2016-05-05 14:15:46 +00:00
Daniel Sanders
fd238b0ebd [mips][ias] Only round section sizes when explicitly requested.
As requested by Rafael Espindola in his post-commit comments on r268036. This
makes the previous behaviour the default while still allowing verification of
IAS.

llvm-svn: 268496
2016-05-04 13:21:06 +00:00
Zlatko Buljan
3153f38fd5 [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions
Differential Revision: http://reviews.llvm.org/D19857

llvm-svn: 268491
2016-05-04 12:02:12 +00:00
Daniel Sanders
be0ced1166 [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.
Summary:
This is much closer to the way MIPS relocation expressions work
(%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the
various bodges in MipsAsmParser::evaluateRelocExpr().

Removing those bodges ensures that the constant stored in MCValue is the
full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used
to correct the %hi/%lo matching needed to sort the relocation table correctly.

As part of this:
* Gave MCExpr::print() the ability to omit parenthesis when emitting a
  symbol reference inside a MipsMCExpr operator like %hi(X). Without this
  we print things like %lo(($L1)).
* %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of
  the related special cases have been removed or moved to MipsMCExpr. We
  can remove the rest as we gain support for the less common relocations
  when they are not part of this specific combination.
* Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion
  with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_').
* fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical
  and merged into fixup_Mips_GOT.
* MO_GOT16 and MO_GOT turned out to be identical and have been merged into
  MO_GOT.
* VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they
  have been merged into MEK_GOT

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19716

llvm-svn: 268379
2016-05-03 13:35:44 +00:00
Daniel Sanders
035784dd96 [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.
Summary:
This removes the temporary call to isIntegratedAssemblerRequired() which was
added recently. It's effect is now acheived directly in the MipsTargetStreamer
hierarchy.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19715

llvm-svn: 268058
2016-04-29 16:16:49 +00:00