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Commit Graph

42029 Commits

Author SHA1 Message Date
Dan Gohman
e49a93ccea Disable constant-offset folding for PowerPC, as the PowerPC target
isn't yet prepared for it.

llvm-svn: 57886
2008-10-21 03:41:46 +00:00
Dan Gohman
847a83dbad Don't create TargetGlobalAddress nodes with offsets that don't fit
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.

Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.

llvm-svn: 57885
2008-10-21 03:38:42 +00:00
Dan Gohman
281881b8e2 Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:

        ucomisd %xmm1, %xmm0
        setne   %al
        setp    %cl
        orb     %al, %cl
        jne     .LBB4_2

it now emits this:

        ucomisd %xmm1, %xmm0
        jne     .LBB4_2
        jp      .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.

llvm-svn: 57873
2008-10-21 03:29:32 +00:00
Dan Gohman
d692070372 When the coalescer is doing rematerializing, have it remove
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.

llvm-svn: 57872
2008-10-21 03:24:31 +00:00
Dan Gohman
d9b79484e0 Make the NaN test come second, heuristically assuming
that NaNs are less common.

llvm-svn: 57871
2008-10-21 03:12:54 +00:00
Dan Gohman
a480933bbd Use Function::getEntryBlock() instead of Function::front(), for clarity.
llvm-svn: 57870
2008-10-21 03:10:28 +00:00
Oscar Fuentes
912b6c40d7 CMake: updated lib/CodeGen/CMakeLists.txt
llvm-svn: 57869
2008-10-21 02:37:50 +00:00
Dan Gohman
080dca2129 Fix a bug that prevented llvm-extract -delete from working.
llvm-svn: 57864
2008-10-21 01:08:07 +00:00
Chris Lattner
c4a880e03c Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts
for strange asm conditions earlier.  In this case, we have a
double being passed in an integer reg class.  Convert to like
sized integer register so that we allocate the right number 
for the class (two i32's for the f64 in this case).

llvm-svn: 57862
2008-10-21 00:45:36 +00:00
Evan Cheng
1bc92a1aa6 Add skeleton for the pre-register allocation live interval splitting pass.
llvm-svn: 57847
2008-10-20 21:44:59 +00:00
Jim Grosbach
1de8b23129 Update the stub and callback code to handle lazy compilation. The stub
is re-written by the callback to branch directly to the compiled code
in future invocations.

Added back in range-based memory permission functions for the updating of
the stub on Darwin.

llvm-svn: 57846
2008-10-20 21:39:23 +00:00
Dan Gohman
204cc4e5ff Fast-isel no longer an experiment.
llvm-svn: 57845
2008-10-20 21:30:12 +00:00
Evan Cheng
c4d1fb1435 Add a register class -> virtual registers map.
llvm-svn: 57844
2008-10-20 20:03:28 +00:00
Evan Cheng
9d9f1ff960 This forward declaration is unnecessary.
llvm-svn: 57843
2008-10-20 20:02:17 +00:00
Duncan Sands
9a3acf8d88 Support operations like fp_to_uint with a vector
result type when the result type is legal but
not the operand type.  Add additional support
for EXTRACT_SUBVECTOR and CONCAT_VECTORS,
needed to handle such cases.

llvm-svn: 57840
2008-10-20 16:31:21 +00:00
Duncan Sands
16503c7e76 Teach getTypeToTransformTo to return something
sensible for vectors being scalarized.  Note
that this method can't return anything very
sensible when splitting non-power-of-two vectors.

llvm-svn: 57839
2008-10-20 16:24:25 +00:00
Duncan Sands
53a9bbae16 LegalizeTypes support for atomic operation promotion.
llvm-svn: 57838
2008-10-20 16:17:42 +00:00
Duncan Sands
e2c4d654e3 Use DAG.getIntPtrConstant rather than DAG.getConstant
with TLI.getPointerTy for a small simplification.

llvm-svn: 57837
2008-10-20 16:14:43 +00:00
Duncan Sands
b912b4c4c4 Always use either MVT::i1 or getSetCCResultType for
the condition of a SELECT node.  Make sure that the
correct extension type (any-, sign- or zero-extend)
is used.

llvm-svn: 57836
2008-10-20 16:13:04 +00:00
Duncan Sands
81b834c160 Formatting - no functional change.
llvm-svn: 57834
2008-10-20 16:06:47 +00:00
Duncan Sands
1872cc22b0 Don't use a random type for the select condition,
use an MVT::i1 and simplify the code while there.

llvm-svn: 57833
2008-10-20 16:04:57 +00:00
Dan Gohman
1c36874fdd Fix a typo in a comment.
llvm-svn: 57832
2008-10-20 15:58:02 +00:00
Duncan Sands
98fc39f607 Have X86 custom lowering for LegalizeTypes use
LowerOperation if it doesn't know what else to do.
This methods should probably be factorized some,
but this is good enough for the moment.  Have
LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather
than assuming the operand is a BUILD_PAIR (if it
is then getNode will automagically simplify the
EXTRACT_ELEMENT).  This way LowerATOMIC_BINARY_64
usable from LegalizeTypes.

llvm-svn: 57831
2008-10-20 15:56:33 +00:00
Matthijs Kooijman
3f50eb8347 Fix typo in a comment.
llvm-svn: 57829
2008-10-20 11:24:57 +00:00
Matthijs Kooijman
d63d1e317b Remove another stale comment.
llvm-svn: 57828
2008-10-20 11:23:18 +00:00
Matthijs Kooijman
ebb16d8ed5 Remove an inappropriate (probably outdated) comment.
llvm-svn: 57827
2008-10-20 11:21:12 +00:00
Matthijs Kooijman
360091f9fd Fix spelling error.
llvm-svn: 57820
2008-10-20 08:45:34 +00:00
Bill Wendling
ed477995f1 Set N->OperandList to 0 after deletion. Otherwise, it's possible that it will
be either deleted or referenced afterwards.

llvm-svn: 57786
2008-10-19 20:51:12 +00:00
Bill Wendling
980c8ad152 Fix comment. Other formatting changes. No functionality changes.
llvm-svn: 57785
2008-10-19 20:34:04 +00:00
Duncan Sands
0a9525febd Vector shuffle mask elements may be "undef". Handle
this everywhere in LegalizeTypes.

llvm-svn: 57783
2008-10-19 15:00:25 +00:00
Duncan Sands
65f39e9819 Use a legal integer type for vector shuffle mask
elements.  Otherwise LegalizeTypes will, reasonably
enough, legalize the mask, which may result in it
no longer being a BUILD_VECTOR node (LegalizeDAG
simply ignores the legality or not of vector masks).

llvm-svn: 57782
2008-10-19 14:58:05 +00:00
Chris Lattner
c369db13cc Reapply r57699 with a fix to not crash on asms with multiple results. Unlike
the previous patch this one actually passes make check.

"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."

llvm-svn: 57771
2008-10-18 18:49:30 +00:00
Dan Gohman
ea1d0d8823 Don't truncate GlobalAddress offsets to int in debug output.
llvm-svn: 57770
2008-10-18 18:22:42 +00:00
Evan Cheng
e742ce1a58 By min, I mean max.
llvm-svn: 57766
2008-10-18 05:21:37 +00:00
Evan Cheng
cf0977d7b1 When creating intervals, leave min(1, numdefs) holes after each instruction.
llvm-svn: 57765
2008-10-18 05:18:55 +00:00
Mon P Wang
772a4e2594 Make llvm memory barrier available as an intrinsic
llvm-svn: 57750
2008-10-18 02:48:13 +00:00
Dan Gohman
15597f07b2 Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748
2008-10-18 02:06:02 +00:00
Dan Gohman
2eaf4f1c48 Revert r57699. It's causing regressions in
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.

llvm-svn: 57747
2008-10-18 01:03:45 +00:00
Dan Gohman
3386be03ea Use the opcode predicates, instead of duplicating the code.
llvm-svn: 57735
2008-10-17 21:42:45 +00:00
Dan Gohman
ac8c7772ba This is now partly done.
llvm-svn: 57734
2008-10-17 21:39:27 +00:00
Dan Gohman
69ac9cc00f This is done.
llvm-svn: 57733
2008-10-17 21:38:40 +00:00
Dan Gohman
e1e1c5197e Factor out the code for mapping LLVM IR condition opcodes to
ISD condition opcodes into helper functions.

llvm-svn: 57726
2008-10-17 21:16:08 +00:00
Evan Cheng
08d0796cf5 Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.
llvm-svn: 57723
2008-10-17 21:02:22 +00:00
Evan Cheng
e7afdb2a42 Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722
2008-10-17 21:00:09 +00:00
Evan Cheng
7792ca759d Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened.
Patch by Lang Hames!

llvm-svn: 57720
2008-10-17 20:56:41 +00:00
Chris Lattner
75618cbb6f add support for 128 bit aggregates.
llvm-svn: 57715
2008-10-17 19:59:51 +00:00
Bill Wendling
39b0625fe0 The Dwarf writer was comparing mangled and unmangled names for C++ code when we
have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714
2008-10-17 18:48:57 +00:00
Mon P Wang
fdfc9a2c4f Added MemIntrinsicNode which is useful to represent target intrinsics that
touches memory and need an associated MemOperand

llvm-svn: 57712
2008-10-17 18:22:58 +00:00
Dan Gohman
96269ec52a Factor out the code for mapping LLVM IR condition opcodes to
ISD condition opcodes into helper functions.

llvm-svn: 57710
2008-10-17 18:18:45 +00:00
Chris Lattner
d96b8d12bc add support for 128 bit inputs on both x86-64 and x86-32.
llvm-svn: 57709
2008-10-17 18:15:05 +00:00