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4330 Commits

Author SHA1 Message Date
Evan Cheng
0d88ad2de1 Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
 2010-05-20 06:13:19 +00:00
Bob Wilson
2dbe0d9886 Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185
 2010-05-19 23:42:58 +00:00
Evan Cheng
9fe8c861bf Code clean up. 
llvm-svn: 104173
 2010-05-19 22:42:23 +00:00
Evan Cheng
46e08acfa5 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Bob Wilson
ae9655920b When expanding a vector_shuffle, the element type may not be legal and may 
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141
 2010-05-19 18:48:32 +00:00
Evan Cheng
632cb17357 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Evan Cheng
e2980af336 Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Evan Cheng
dae4e9e4bc Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices. 
llvm-svn: 104051
 2010-05-18 20:07:47 +00:00
Evan Cheng
9fc34e676d Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. 
llvm-svn: 104050
 2010-05-18 20:03:28 +00:00
Evan Cheng
39b5115e93 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
llvm-svn: 104004
 2010-05-18 00:03:40 +00:00
Bill Wendling
5a1c9f8d06 - Set the "HasCalls" flag after instruction selection is finished. 
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.

llvm-svn: 103990
 2010-05-17 23:09:50 +00:00
Dale Johannesen
82dfdcdde7 Fix uint64->{float, double} conversion to do rounding correctly in 32-bit. 
The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.

llvm-svn: 103883
 2010-05-15 18:51:12 +00:00
Dale Johannesen
d093363ea5 Improve assertion messages. 
llvm-svn: 103882
 2010-05-15 18:38:02 +00:00
Dan Gohman
4049434a04 Fast ISel trivially coalesces away no-op casts, so check for this when 
setting kill flags.

llvm-svn: 103832
 2010-05-14 22:53:18 +00:00
Dan Gohman
97d22ade75 Don't set kill flags for instructions which the scheduler has cloned. 
llvm-svn: 103827
 2010-05-14 22:01:14 +00:00
Bill Wendling
e346a38ed4 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Dale Johannesen
9f19b6a761 Implement a correct ui64->f32 conversion. The old 
one was subject to double rounding in extreme cases.

llvm-svn: 103744
 2010-05-13 23:50:42 +00:00
Dan Gohman
d7b4c5b82e An Instruction has a trivial kill only if its use is in the same 
basic block.

llvm-svn: 103725
 2010-05-13 19:19:32 +00:00
Dan Gohman
03e407ed83 Add initial kill flag support to FastISel. 
llvm-svn: 103529
 2010-05-11 23:54:07 +00:00
Dan Gohman
2ace137eb9 Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't 
create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.

llvm-svn: 103519
 2010-05-11 21:59:14 +00:00
Duncan Sands
7d5e4152c3 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.

llvm-svn: 103495
 2010-05-11 20:16:09 +00:00
Dan Gohman
ca2df906ae Trim #includes and forward declarations. 
llvm-svn: 103489
 2010-05-11 19:11:43 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Douglas Gregor
2f2491405a Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 
llvm-svn: 103457
 2010-05-11 06:17:44 +00:00
Evan Cheng
de3482f4af Indentation. 
llvm-svn: 103441
 2010-05-10 23:08:19 +00:00
Evan Cheng
df350445c6 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869. 
llvm-svn: 103419
 2010-05-10 19:03:57 +00:00
Duncan Sands
83c7bda62e Add an assertion to catch attempts to access off the end of the array. 
Based on a patch by Javier Martinez.

llvm-svn: 103391
 2010-05-10 04:54:28 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem, 
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
 2010-05-07 22:19:08 +00:00
Devang Patel
3c2f4664fc Verify variable directly. 
llvm-svn: 103305
 2010-05-07 22:04:20 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending 
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
 2010-05-07 21:35:53 +00:00
Dan Gohman
4d75cfcc09 Transfer debug location information from PHI nodes to resulting 
lowered copies.

llvm-svn: 103228
 2010-05-07 01:10:20 +00:00
Dan Gohman
6650aa28f1 Print debug information for SDNodes. 
llvm-svn: 103227
 2010-05-07 01:09:21 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Dan Gohman
f7bc83b2ed In bottom-up mode, defer the materialization of local constant values. 
llvm-svn: 103139
 2010-05-06 00:02:14 +00:00
Dan Gohman
180422793f Add an "IsBottomUp" member function to FastISel, which will be used to 
support a new bottom-up mode.

llvm-svn: 103138
 2010-05-05 23:58:35 +00:00
Devang Patel
041a8fa086 Use getValue() for PHINodes when direct NodeMap access does not work. 
llvm-svn: 103126
 2010-05-05 22:29:00 +00:00
Evan Cheng
66ef3ff9c7 Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489 
llvm-svn: 102993
 2010-05-04 00:58:39 +00:00
Evan Cheng
f7b5c86a0b Teach scheduler about REG_SEQUENCE. 
llvm-svn: 102984
 2010-05-04 00:22:40 +00:00
Dan Gohman
50b08bfbc8 Re-enable isel kill flags, now that the local allocator is ignoring them. 
llvm-svn: 102981
 2010-05-04 00:12:15 +00:00
Dan Gohman
8bfd5f99b5 Factor out FastISel's code for materializing constants and other values 
in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.

llvm-svn: 102975
 2010-05-03 23:36:34 +00:00
Anton Korobeynikov
a3726088fa Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), 
when needed. This fixes PR7001

llvm-svn: 102838
 2010-05-01 12:52:34 +00:00
Dan Gohman
ada97c52fe Remove the code for special-casing byval for fast-isel. SelectionDAG 
handles argument lowering anyway, so there's no need for special
casing here.

llvm-svn: 102828
 2010-05-01 02:44:23 +00:00
Dan Gohman
fb5d6a5d70 Re-disable kill flags, as there is more trouble. 
llvm-svn: 102826
 2010-05-01 01:57:56 +00:00
Dan Gohman
5fc96b81ec Re-enable kill flags from SelectionDAGISel, with a fix: don't 
try to put a kill flag on a DBG_INFO instruction.

llvm-svn: 102820
 2010-05-01 00:50:53 +00:00
Dan Gohman
1a6c7dfb3e Fix whitespace. 
llvm-svn: 102817
 2010-05-01 00:33:28 +00:00
Dan Gohman
37fe41a8c0 Don't pass SDValues by non-const reference unless they may be 
modified.

llvm-svn: 102816
 2010-05-01 00:33:16 +00:00
Dan Gohman
0561bd78d0 Reorgnaize more switch code lowering to clean up some tricky 
code, and to eliminate the need for the SelectionDAGBuilder
state to be live during CodeGenAndEmitDAG calls.

Call SDB->clear() before CodeGenAndEmitDAG calls instead of
before it, and move the CurDAG->clear() out of SelectionDAGBuilder,
which doesn't own the DAG, and into CodeGenAndEmitDAG.

llvm-svn: 102814
 2010-05-01 00:25:44 +00:00
Dan Gohman
d59de31ce2 Delete the EdgeMapping variable itself. 
llvm-svn: 102810
 2010-05-01 00:02:20 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Bill Wendling
95a4929ac7 EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the 
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.

llvm-svn: 102791
 2010-04-30 22:19:17 +00:00