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2708 Commits

Author SHA1 Message Date
Craig Topper
56cbdd4cd7 Remove 'XXXRegisterClass' from tablegen output. Targets should use '&XXXRegClass' instead. 
llvm-svn: 155270
 2012-04-21 01:49:25 +00:00
Andrew Trick
155245effc TableGen'd RegPressure: Added getPressureSetName. 
llvm-svn: 155234
 2012-04-20 20:44:58 +00:00
Jim Grosbach
0cd0534390 TableGen support for auto-generating assembly two-operand aliases. 
Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
  add {Rd}, Rn, Rm  // Rd is optional and is the same as Rn if omitted.

The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.

rdar://11255754

llvm-svn: 155172
 2012-04-19 23:59:23 +00:00
Jim Grosbach
e8c60733b9 Use a SmallVector instead of std::vector for ResOperands. 
There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.

llvm-svn: 155143
 2012-04-19 17:52:34 +00:00
Jim Grosbach
d335490731 Update some internal naming conventions to modern style. 
llvm-svn: 155142
 2012-04-19 17:52:32 +00:00
Craig Topper
626573d98d Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away. 
llvm-svn: 155104
 2012-04-19 06:52:06 +00:00
Jim Grosbach
013a59646b Fix typo. 
llvm-svn: 155075
 2012-04-18 23:46:25 +00:00
Jim Grosbach
f77ed6f9c3 Revert "Replace some uses of std:map<std::string,...> with StringMap." 
StringMap iterators are not deterministic, and that's more important
here than speed or memory.

llvm-svn: 155039
 2012-04-18 20:24:49 +00:00
Benjamin Kramer
2991126d0d tblgen: remove duplicated newlines. 
llvm-svn: 155038
 2012-04-18 19:22:47 +00:00
Jim Grosbach
050ec9bce7 Replace some uses of std:map<std::string,...> with StringMap. 
llvm-svn: 155037
 2012-04-18 19:13:59 +00:00
Jim Grosbach
e29486798c Use SmallVector for the requirements on an InstAlias. 
llvm-svn: 155034
 2012-04-18 19:02:43 +00:00
Jim Grosbach
ae2ac1f597 Tidy up. Formatting. 
llvm-svn: 155032
 2012-04-18 18:56:33 +00:00
Jim Grosbach
26c6c85855 Move a few more warnings to use PrintWarning(). 
llvm-svn: 155027
 2012-04-18 18:39:31 +00:00
Jim Grosbach
f8c6a6ba04 Tidy up. No need for a Twine here, as it's just constants. 
llvm-svn: 155026
 2012-04-18 18:39:27 +00:00
Jim Grosbach
5e14805a0f Formatting. 
llvm-svn: 155025
 2012-04-18 18:39:23 +00:00
Jim Grosbach
e846a32427 Tidy up. Add a '.' at the end of the sentence. 
llvm-svn: 155024
 2012-04-18 18:39:19 +00:00
Jim Grosbach
78b59b30e7 Clean up warning text. Remove extraneous prefix. 
llvm-svn: 155015
 2012-04-18 18:09:50 +00:00
Jim Grosbach
3c537f8fb4 TableGen use PrintWarning rather than fprintf(stderr,...) for warnings. 
That way we get source line number information from the diagnostics.

llvm-svn: 155014
 2012-04-18 17:46:41 +00:00
Silviu Baranga
8e0ebc8ed7 Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction. 
llvm-svn: 155000
 2012-04-18 13:02:55 +00:00
Jim Grosbach
d32ea4a8a9 Sanity check error handling for TokenAlias. 
llvm-svn: 154951
 2012-04-17 21:23:52 +00:00
Jim Grosbach
ced1f200a3 Tidy up. 80 columns. 
llvm-svn: 154881
 2012-04-17 00:01:04 +00:00
Craig Topper
da52eeedcb Fix target specific intrinsic handling to adjust intrinsic number before doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542 
llvm-svn: 154658
 2012-04-13 06:14:57 +00:00
Jim Grosbach
8327980405 Remove incorrect comment. 
llvm-svn: 154533
 2012-04-11 21:09:54 +00:00
Jim Grosbach
80c9f4d837 Tidy up. Remove hard tab characters. 
llvm-svn: 154532
 2012-04-11 21:02:33 +00:00
Jim Grosbach
51aa44347a Tidy up. Whitespace. 
llvm-svn: 154531
 2012-04-11 21:02:30 +00:00
Andrew Trick
6d7aff8241 TableGen's regpressure: emit per-registerclass weight limits. 
llvm-svn: 154518
 2012-04-11 18:16:28 +00:00
Andrew Trick
2628429e92 TableGen'd regpressure: register unit set pruning. 
The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.

llvm-svn: 154510
 2012-04-11 17:35:26 +00:00
Andrew Trick
a2a5c3bb71 Tablegen'd regpressure: emit the weighted pressure limit. 
llvm-svn: 154477
 2012-04-11 04:31:33 +00:00
Andrew Trick
ccfe0f1fc6 Table-generated register pressure fixes. 
Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.

llvm-svn: 154474
 2012-04-11 03:19:15 +00:00
Andrew Trick
0c60300f39 TableGen/reginfo potential bug: typo from previous checkin. 
llvm-svn: 154452
 2012-04-10 23:53:32 +00:00
Andrew Trick
360c19ad86 Fix for register pressure tables. 
Recent refactoring introduced a bug. Fix: added buildRegUnitSets.

llvm-svn: 154382
 2012-04-10 03:36:49 +00:00
Andrew Trick
218abb3a9c Use std::includes instead of my own implementation. 
Jakob's review.

llvm-svn: 154377
 2012-04-10 03:12:29 +00:00
Andrew Trick
6b7d15e240 Added register unit sets to the target description. 
This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

llvm-svn: 154374
 2012-04-10 02:25:24 +00:00
Andrew Trick
f73fa6bef2 Added register unit weights to the target description. 
This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.

llvm-svn: 154373
 2012-04-10 02:25:21 +00:00
Andrew Trick
7b51eb5f5e Fix header comment 
llvm-svn: 154372
 2012-04-10 02:25:18 +00:00
Craig Topper
2a4fe8b344 Convert assert(false) followed by a return to llvm_unreachable 
llvm-svn: 153997
 2012-04-04 04:55:46 +00:00
Craig Topper
b4929c0302 Tidy up spacing in some tablegen outputs. 
llvm-svn: 153937
 2012-04-03 06:52:47 +00:00
Craig Topper
ce6c05e0df Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
llvm-svn: 153935
 2012-04-03 05:20:24 +00:00
Andrew Trick
a1e25f74dd Cleanup set_union usage. The same thing but a bit cleaner now. 
llvm-svn: 153922
 2012-04-03 01:35:52 +00:00
Andrew Trick
a92546a4bb Use std::set_union instead of nasty custom code. 
I just noticed Jakob's examples of the proper application of
std::set... routines.

llvm-svn: 153918
 2012-04-03 00:47:23 +00:00
Silviu Baranga
af228a1538 Second part for the 153874 one 
llvm-svn: 153875
 2012-04-02 15:46:46 +00:00
Benjamin Kramer
d960cf6265 Emit the asm writer's mnemonic table with SequenceToOffsetTable. 
This way we can get AVX v-prefixed instructions tail merged with the normal insns.

llvm-svn: 153869
 2012-04-02 09:13:46 +00:00
Craig Topper
52dc5e74e5 Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. 
llvm-svn: 153865
 2012-04-02 07:48:39 +00:00
Craig Topper
fe02cb5e8b Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
llvm-svn: 153863
 2012-04-02 07:01:04 +00:00
Craig Topper
949f3bef7a Use SequenceToOffsetTable to generate instruction name table for AsmWriter. 
llvm-svn: 153857
 2012-04-02 00:47:39 +00:00
Craig Topper
56bc73a030 Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. 
llvm-svn: 153841
 2012-04-01 18:14:14 +00:00
Benjamin Kramer
84a17ab494 Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup. 
This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

llvm-svn: 153837
 2012-04-01 14:23:58 +00:00
Andrew Trick
e5028d95da comment typo 
llvm-svn: 153796
 2012-03-31 02:39:17 +00:00
Andrew Trick
f1fa07f326 Introduce Register Units: Give each leaf register a number. 
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

llvm-svn: 153794
 2012-03-31 01:35:59 +00:00
Benjamin Kramer
dbd6a33c45 Rip out emission of the regIsInRegClass function for the asm printer. 
It's slow, bloated and completely redundant with MCRegisterClass::contains.

llvm-svn: 153782
 2012-03-30 23:13:40 +00:00