Evan Cheng
10a350fa89
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
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llvm-svn: 55840
2008-09-05 17:24:07 +00:00
Dan Gohman
29cba19a2a
Check a comparion's operand type for legality before
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expanding its operands.
llvm-svn: 55820
2008-09-05 01:33:56 +00:00
Dan Gohman
121baa1723
Fix X86FastISel code for comparisons and conditional branches
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to check the result of getRegForValue before using it, and
to check for illegal operand types.
llvm-svn: 55819
2008-09-05 01:15:35 +00:00
Dan Gohman
783f38e056
X86FastISel support for conditional branches.
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llvm-svn: 55816
2008-09-05 01:06:14 +00:00
Owen Anderson
6d5b72d45a
Add initial support for selecting constant materializations that require constant
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pool loads on X86 in fast isel. This isn't actually used yet.
llvm-svn: 55814
2008-09-05 00:06:23 +00:00
Dan Gohman
88c3de638e
X86FastISel support for ICmpInst and FCmpInst.
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llvm-svn: 55811
2008-09-04 23:26:51 +00:00
Evan Cheng
bd15e330d0
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
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llvm-svn: 55807
2008-09-04 22:59:58 +00:00
Devang Patel
f3770334a9
If function notes say optimize for size, then adjust alignment.
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llvm-svn: 55794
2008-09-04 21:03:41 +00:00
Dan Gohman
e1f9be27bc
Tidy up several unbeseeming casts from pointer to intptr_t.
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llvm-svn: 55779
2008-09-04 17:05:41 +00:00
Owen Anderson
cd3ee9198d
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
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llvm-svn: 55777
2008-09-04 16:48:33 +00:00
Dan Gohman
7ee14837e6
Clean up uses of TargetLowering::getTargetMachine.
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llvm-svn: 55769
2008-09-04 15:39:15 +00:00
Owen Anderson
35485dbae3
Add a first attempt at implementing stores for X86 fast isel using target hooks.
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Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
Evan Cheng
9c728a557d
Load from GV stub should be locally CSE'd.
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llvm-svn: 55763
2008-09-04 06:18:33 +00:00
Evan Cheng
53ce5fa5ce
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
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llvm-svn: 55756
2008-09-04 01:04:15 +00:00
Dale Johannesen
9e4d101fab
Add intrinsics for log, log2, log10, exp, exp2.
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No functional change (and no FE change to generate them).
llvm-svn: 55753
2008-09-04 00:47:13 +00:00
Dan Gohman
18cc2a26df
Create HandlePHINodesInSuccessorBlocksFast, a version of
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HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
llvm-svn: 55746
2008-09-03 23:12:08 +00:00
Evan Cheng
942d55dd92
Add X86 target hook to implement load (even from GlobalAddress).
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llvm-svn: 55693
2008-09-03 06:44:39 +00:00
Ted Kremenek
b7236d215b
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
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llvm-svn: 55687
2008-09-03 02:54:11 +00:00
Evan Cheng
4cef3f6ce1
Unbreak fast isel.
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llvm-svn: 55685
2008-09-03 01:04:47 +00:00
Evan Cheng
43c7084625
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
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llvm-svn: 55679
2008-09-03 00:03:49 +00:00
Dale Johannesen
46f19abcec
Fix some bugs in the code sequences for atomics.
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llvm-svn: 55643
2008-09-02 20:30:23 +00:00
Evan Cheng
126bd60288
Add Mac OS X compatible JIT callback routine.
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llvm-svn: 55625
2008-09-02 07:49:03 +00:00
Evan Cheng
e97c48a34a
Revamp ARM JIT.
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llvm-svn: 55624
2008-09-02 06:52:38 +00:00
Evan Cheng
9817be2f96
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
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llvm-svn: 55623
2008-09-02 06:51:36 +00:00
Evan Cheng
738426a2a1
Control flow instruction encodings.
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llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909
AXI2 and AXI3 instruction encodings.
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llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627
Reorganize instruction formats again; AXI1 encoding.
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llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42
Reorganize some instruction format definitions. No functionality change.
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llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e
Rest of addrmode2 instruction encodings.
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llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng
94f3d276c6
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
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llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Gabor Greif
7db742d8c2
fix a bunch of 80-col violations
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llvm-svn: 55588
2008-08-31 15:37:04 +00:00
Bill Wendling
297eb080b6
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
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instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
Bill Wendling
8faa2f3ec4
Expand for ROTR with MVT::i64.
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Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
Gabor Greif
8fa04b6eb0
fix some 80-col violations
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llvm-svn: 55565
2008-08-30 10:09:02 +00:00
Evan Cheng
c3c439a624
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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llvm-svn: 55562
2008-08-30 08:54:22 +00:00
Evan Cheng
4bc8c9652e
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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llvm-svn: 55558
2008-08-30 02:03:58 +00:00
Dale Johannesen
1cfbb25e75
Add ppc partial-word ATOMIC_CMP_SWAP.
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llvm-svn: 55554
2008-08-30 00:08:53 +00:00
Evan Cheng
c1c53221c5
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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llvm-svn: 55553
2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08
Use static_cast instead of C style cast.
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llvm-svn: 55552
2008-08-29 23:21:31 +00:00
Evan Cheng
17382f9ffb
Backing out 55521. Not safe.
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llvm-svn: 55548
2008-08-29 22:13:21 +00:00
Dale Johannesen
bc977ce106
Add partial word version of ATOMIC_SWAP.
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llvm-svn: 55546
2008-08-29 18:29:46 +00:00
Owen Anderson
3aa3841da2
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
Evan Cheng
3fb02ae0b6
TableGen'ing instruction encodings.
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llvm-svn: 55533
2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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llvm-svn: 55531
2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng
f90bc9a050
More refactoring.
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llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Evan Cheng
cdd06ba3f4
Swap fp comparison operands and change predicate to allow load folding.
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llvm-svn: 55521
2008-08-28 23:48:31 +00:00