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Commit Graph

122727 Commits

Author SHA1 Message Date
David Blaikie
10d73dfd9d Fix -Wdeprecated regarding ORC copying ValueMaterializers
As usual, this is a polymorphic hierarchy without polymorphic ownership,
so simply make the dtor protected non-virtual, protected default copy
ctor/assign, and make derived classes final. The derived classes will
pick up correct default public copy ops (and dtor) implicitly.

(wish I could add -Wdeprecated to the build, but last time I tried it
triggered on some system headers I still need to look into/figure out)

llvm-svn: 250747
2015-10-19 22:15:55 +00:00
Michael Liao
5efcb99302 [InstCombine] Optimize icmp of inc/dec at RHS
Allow LLVM to optimize the sequence like the following:

  %inc = add nsw i32 %i, 1
  %cmp = icmp slt %n, %inc

into:

  %cmp = icmp sle i32 %n, %i

The case is not handled previously due to the complexity of compuation of %n.
Hence, LLVM cannot swap operands of icmp accordingly.

llvm-svn: 250746
2015-10-19 22:08:14 +00:00
Duncan P. N. Exon Smith
61308781b2 Vectorize: Remove implicit ilist iterator conversions, NFC
Besides the usual, I finally added an overload to
`BasicBlock::splitBasicBlock()` that accepts an `Instruction*` instead
of `BasicBlock::iterator`.  Someone can go back and remove this overload
later (after updating the callers I'm going to skip going forward), but
the most common call seems to be
`BB->splitBasicBlock(BB->getTerminator(), ...)` and I'm not sure it's
better to add `->getIterator()` to every one than have the overload.
It's pretty hard to get the usage wrong.

llvm-svn: 250745
2015-10-19 22:06:09 +00:00
Sanjay Patel
659d8f6866 [CGP] transform select instructions into branches and sink expensive operands
This was originally checked in at r250527, but reverted at r250570 because of PR25222.
There were at least 2 problems: 
1. The cost check was checking for an instruction with an exact cost of TCC_Expensive;
that should have been >=.
2. The cause of the clang stage 1 failures was illegally sinking 'call' instructions;
we can't sink instructions that may have side effects / are not safe to execute speculatively.

Fixed those conditions in sinkSelectOperand() and added test cases.

Original commit message:
This is a follow-up to the discussion in D12882.

Ideally, we would like SimplifyCFG to be able to form select instructions even when the operands
are expensive (as defined by the TTI cost model) because that may expose further optimizations.
However, we would then like a later pass like CodeGenPrepare to undo that transformation if the
target would likely benefit from not speculatively executing an expensive op (this patch).

Once we have this safety mechanism in place, we can adjust SimplifyCFG to restore its
select-formation behavior that changed with r248439.

Differential Revision: http://reviews.llvm.org/D13297

llvm-svn: 250743
2015-10-19 21:59:12 +00:00
Duncan P. N. Exon Smith
4be8cb04fe X86: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250741
2015-10-19 21:48:29 +00:00
Lang Hames
e46a5d118c [RuntimeDyld][COFF] Fix some endianness issues, re-enable the regression test.
llvm-svn: 250733
2015-10-19 20:37:52 +00:00
Owen Anderson
c398b9a4d4 Restore the original behavior of SelectionDAG::getTargetIndex().
It looks like an extra negation snuck in as apart of restoring it.

llvm-svn: 250726
2015-10-19 19:27:40 +00:00
Krzysztof Parzyszek
62bb5a1179 [Hexagon] Remove unnecessary argument sign extends
llvm-svn: 250724
2015-10-19 19:10:48 +00:00
Teresa Johnson
4655ffb0a6 Pass FunctionInfoIndex by reference to WriteFunctionSummaryToFile (NFC)
Implemented suggestion by dblakie in review for r250704.

llvm-svn: 250723
2015-10-19 19:06:06 +00:00
Lang Hames
0b6ee135ac [Orc] Add explicit move constructor and assignment operator to make MSVC happy.
llvm-svn: 250722
2015-10-19 18:59:22 +00:00
Benjamin Kramer
64bcbe6d8e Add missing override noticed by Clang's -Winconsistent-missing-override.
llvm-svn: 250720
2015-10-19 18:41:23 +00:00
Jun Bum Lim
16578167d7 [AArch64]Merge halfword loads into a 32-bit load
Convert two halfword loads into a single 32-bit word load with bitfield extract
instructions. For example :
  ldrh w0, [x2]
  ldrh w1, [x2, #2]
becomes
  ldr w0, [x2]
  ubfx w1, w0, #16, #16
  and  w0, w0, #ffff

llvm-svn: 250719
2015-10-19 18:34:53 +00:00
Krzysztof Parzyszek
f11fad31d2 [Hexagon] Fix debug information for local objects
- Isolate the check for the existence of a stack frame into hasFP.
- Implement getFrameIndexReference for DWARF address computation.
- Use getFrameIndexReference for offset computation in eliminateFrameIndex.
- Preserve debug information for dynamically allocated stack objects.
- Prefer FP to access local objects at -O0.
- Add experimental code to skip allocframe when not strictly necessary
  (disabled by default).

llvm-svn: 250718
2015-10-19 18:30:27 +00:00
Benjamin Kramer
2339b6e6ad Put back SelectionDAG::getTargetIndex.
While technically this is untested dead code, it has out-of-tree users.
This reverts a part of r250434.

llvm-svn: 250717
2015-10-19 18:26:16 +00:00
Lang Hames
d245affa6e [Orc] Lambda needs to capture 'this'.
llvm-svn: 250716
2015-10-19 17:53:43 +00:00
Lang Hames
340b0e68f4 [Orc] Remove extraneous semicolon that found its way into r250712.
llvm-svn: 250715
2015-10-19 17:49:37 +00:00
Krzysztof Parzyszek
1d955c1e56 [Hexagon] Delay emission of CFI instructions
Emit the CFI instructions after all code transformation have been done.
This will avoid any interference between CFI instructions and packetization.

llvm-svn: 250714
2015-10-19 17:46:01 +00:00
Matthias Braun
c2e8632c14 Revert "RegisterPressure: allocatable physreg uses are always kills"
This reverts commit r250596.

Reverted for now as the commit triggers assert in the AMDGPU target
pending investigation.

llvm-svn: 250713
2015-10-19 17:44:22 +00:00
Lang Hames
4bba9adcc4 [Orc] Add support for emitting indirect stubs directly into the JIT target's
memory, rather than representing the stubs in IR. Update the CompileOnDemand
layer to use this functionality.

Directly emitting stubs is much cheaper than building them in IR and codegen'ing
them (see below). It also plays well with remote JITing - stubs can be emitted
directly in the target process, rather than having to send them over the wire.

The downsides are:

(1) Care must be taken when resolving symbols, as stub symbols are held in a
    separate symbol table. This is only a problem for layer writers and other
    people using this API directly. The CompileOnDemand layer hides this detail.

(2) Aliases of function stubs can't be symbolic any more (since there's no
    symbol definition in IR), but must be converted into a constant pointer
    expression. This means that modules containing aliases of stubs cannot be
    cached. In practice this is unlikely to be a problem: There's no benefit to
    caching such a module anyway.

On balance I think the extra performance is more than worth the trade-offs: In a
simple stress test with 10000 dummy functions requiring stubs and a single
executed "hello world" main function, directly emitting stubs reduced user time
for JITing / executing by over 90% (1.5s for IR stubs vs 0.1s for direct
emission).

llvm-svn: 250712
2015-10-19 17:43:51 +00:00
Teresa Johnson
0fb3f39b16 Convert gold-plugin unnecessary unique_ptr into local (NFC)
llvm-svn: 250704
2015-10-19 15:23:03 +00:00
Teresa Johnson
e92d7c468f Fix required library for r250699 to BitWriter instead of BitReader.
This should fix the mingw3 bot failure.

llvm-svn: 250703
2015-10-19 15:21:46 +00:00
Teresa Johnson
422fa9feaa Fix windows bot failures from r250699 by removing "/" from expected path
in test output.

llvm-svn: 250701
2015-10-19 15:19:02 +00:00
Teresa Johnson
8fa2a4762b llvm-lto support for generating combined function indexes
Summary:
This patch adds support to llvm-lto that mirrors the support added by
r249270 to the gold plugin. This enables better testing of combined
index generation for ThinLTO.

Added a new test, and this support will be used in the test in D13515.

Reviewers: joker.eph

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13847

llvm-svn: 250699
2015-10-19 14:30:44 +00:00
Benjamin Kramer
170c107663 Remove CRLF newlines. NFC.
llvm-svn: 250698
2015-10-19 13:05:25 +00:00
Asiri Rathnayake
8d48a252a1 Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions
The mapping of these two intrinsics in ARMInstrInfo.td had a small
omission which lead to their operands not being validated/transformed
before being lowered into usat and ssat instructions. This can cause
incorrect instructions to be emitted.

I've also added tests for the remaining two saturating arithmatic
intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing
codegen tests.

llvm-svn: 250697
2015-10-19 11:44:24 +00:00
James Molloy
570047b4e8 [GlobalsAA] Fix a really horrible iterator invalidation bug
We were keeping a reference to an object in a DenseMap then mutating it. At the end of the function we were attempting to clone that reference into other keys in the DenseMap, but DenseMap may well decide to resize its hashtable which would invalidate the reference!

It took an extremely complex testcase to catch this - many thanks to Zhendong Su for catching it in PR25225.

This fixes PR25225.

llvm-svn: 250692
2015-10-19 08:54:59 +00:00
Elena Demikhovsky
2e0208e770 Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().
Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case.

Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces.

Differential Revision: http://reviews.llvm.org/D13850

llvm-svn: 250686
2015-10-19 07:43:38 +00:00
Zlatko Buljan
56aeea0467 [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130

llvm-svn: 250685
2015-10-19 07:16:26 +00:00
Zlatko Buljan
51aca82162 [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions
Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
2015-10-19 06:34:44 +00:00
Xinliang David Li
9a04c1cb96 [PGO] Eliminate prof data register calls on FreeBSD platform
This is a follow up patch of r250199 after verifying the start/stop
section symbols work as spected on FreeBSD.

llvm-svn: 250679
2015-10-19 04:17:10 +00:00
Jakub Staszak
c9f385dfda Preserve CFG in MergedLoadStoreMotion. This fixes PR24426.
llvm-svn: 250660
2015-10-18 19:34:10 +00:00
Rafael Espindola
e895ac195c Add hashing and DenseMapInfo for ArrayRef
Sometimes it is more natural to use a ArrayRef<uint8_t> than a StringRef to
represent a range of bytes that is not, semantically, a string.

This will be used in lld in a sec.

llvm-svn: 250658
2015-10-18 14:04:56 +00:00
Simon Pilgrim
d6af85a509 [X86][SSE] Add vector bit rotation tests.
llvm-svn: 250656
2015-10-18 12:54:37 +00:00
Simon Pilgrim
023d75d398 Use SDValue bool check. NFCI.
llvm-svn: 250653
2015-10-18 12:33:54 +00:00
Simon Pilgrim
9766a65452 Move one-use variable inside test. NFC.
llvm-svn: 250651
2015-10-18 11:47:23 +00:00
Asaf Badouh
381b11d5f2 [X86][AVX512DQ] add scalar fpclass
Differential Revision: http://reviews.llvm.org/D13769

llvm-svn: 250650
2015-10-18 11:04:38 +00:00
Igor Breger
c4af5733a0 AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instruction
Differential Revision: http://reviews.llvm.org/D13632

llvm-svn: 250649
2015-10-18 09:56:39 +00:00
Craig Topper
e8b9c46ea0 [Sparc] Use MCPhysReg instead of unsigned to size static arrays of registers. Should reduce the table size.
llvm-svn: 250644
2015-10-18 05:29:05 +00:00
Craig Topper
9cb32a6d3f Use array_lengthof. NFC
llvm-svn: 250643
2015-10-18 05:15:38 +00:00
Craig Topper
c8409f4435 Make a bunch of static arrays const.
llvm-svn: 250642
2015-10-18 05:15:34 +00:00
Lang Hames
544dee31ad [RuntimeDyld] Add support for absolute symbols.
llvm-svn: 250639
2015-10-18 01:41:37 +00:00
Xinliang David Li
7785bb6a4d Minor Instr PGO code restructuring
1. Key constant values (version, magic) and data structures related to raw and 
   indexed profile format are moved into one centralized file: InstrProf.h.
2. Utility function such as MD5Hash computation is also moved to the common 
   header to allow sharing with other components in the future.
3. A header data structure is introduced for Indexed format so that the reader
   and writer can always be in sync.
4. Added some comments to document different places where multiple definition
   of the data structure must be kept in sync (reader/writer, runtime, lowering 
   etc).  No functional change is intended.

Differential Revision:  http://reviews.llvm.org/D13758

llvm-svn: 250638
2015-10-18 01:02:29 +00:00
Sanjoy Das
b98ecd3f49 [SCEV] Fix whitespace issues and remove extra braces; NFC
llvm-svn: 250636
2015-10-18 00:29:27 +00:00
Sanjoy Das
50512a9a28 [SCEV] Use std::all_of and std::any_of; NFC
llvm-svn: 250635
2015-10-18 00:29:23 +00:00
Sanjoy Das
08660450fd [SCEV] Use auto where it helps remove line breaks; NFC
llvm-svn: 250634
2015-10-18 00:29:20 +00:00
Sanjoy Das
c8d2bcdfc3 [SCEV] Use range for loops; NFC
llvm-svn: 250633
2015-10-18 00:29:16 +00:00
Craig Topper
fdfcb9c13b Use std::find instead of manual loop.
llvm-svn: 250624
2015-10-17 21:32:28 +00:00
Craig Topper
c599e54974 Use std::is_sorted to replace a custom version. Also replace a comparison predicate struct with a lambda.
llvm-svn: 250623
2015-10-17 21:32:26 +00:00
Simon Pilgrim
a6b49e0950 [X86][XOP] Add VPROT instruction opcodes
Added X86ISD opcodes for VPROT vector rotate by variable and by immediate.

llvm-svn: 250620
2015-10-17 19:04:24 +00:00
Craig Topper
164e34fdb4 Remove unnecessary 'const' pointed out by David Blaikie.
llvm-svn: 250619
2015-10-17 18:22:46 +00:00