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Commit Graph

6617 Commits

Author SHA1 Message Date
Evan Cheng
f9951d1557 Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.


Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.

llvm-svn: 66875
2009-03-13 07:51:59 +00:00
Chris Lattner
cbbdd230dd generalize the previous code to use the full generality of LEA
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this).  On the example, we now
generate:

_test:
	movl	4(%esp), %eax
	cmpl	$42, (%eax)
	setl	%al
	movzbl	%al, %eax
	leal	4(%eax,%eax,8), %eax
	ret

instead of:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	movl	$4, %ecx
	movl	$13, %eax
	cmovg	%ecx, %eax
	ret

llvm-svn: 66869
2009-03-13 05:53:31 +00:00
Chris Lattner
878d951f8f optimize the case of cond ? 42 : 41 and friends. This compiles the
example to:

_test:
	movl	4(%esp), %eax
	cmpl	$41, (%eax)
	setg	%al
	movzbl	%al, %eax
	orl	$4294967294, %eax
	ret

instead of:

        movl    4(%esp), %eax
        cmpl    $41, (%eax)
	movl	$4294967294, %ecx
	movl	$4294967295, %eax
	cmova	%ecx, %eax
	ret

which is smaller in code size and faster. rdar://6668608

llvm-svn: 66868
2009-03-13 05:22:11 +00:00
Bill Wendling
02a239b837 Temporarily XFAIL this test.
llvm-svn: 66866
2009-03-13 04:37:11 +00:00
Dan Gohman
37d843c129 Enhance address-mode folding of ISD::ADD to handle cases where the
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.

llvm-svn: 66865
2009-03-13 02:25:09 +00:00
Evan Cheng
27be5272b4 Add this test back.
llvm-svn: 66838
2009-03-12 23:01:35 +00:00
Duncan Sands
968939fca2 Revert commit 66140 since it caused several failures
in the Ada testcase.  Reverting this only covers up
the real problem, which is a nasty conceptual difficulty
in the phi elimination pass: when eliminating phi nodes
in landing pads, the register copies need to come before
the invoke, not at the end of the basic block which is
too late...  See PR3784.

llvm-svn: 66826
2009-03-12 21:13:42 +00:00
Evan Cheng
e04a84ed9f Typo.
llvm-svn: 66797
2009-03-12 17:07:39 +00:00
Evan Cheng
45aa89fa9a Fix test after Chris' select changes.
llvm-svn: 66795
2009-03-12 16:10:08 +00:00
Duncan Sands
38860e65b3 Adjust this test for recent sroa improvements.
llvm-svn: 66791
2009-03-12 11:56:12 +00:00
Chris Lattner
26a971c4ec Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.

llvm-svn: 66779
2009-03-12 06:52:53 +00:00
Evan Cheng
46e903d2f6 On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
llvm-svn: 66776
2009-03-12 05:59:15 +00:00
Chris Lattner
a5368fd283 add no-unwind, remove duplicate run line.
llvm-svn: 66775
2009-03-12 05:56:37 +00:00
Chris Lattner
cb52d81eea add nounwinds
llvm-svn: 66773
2009-03-12 05:35:33 +00:00
Dan Gohman
d30e108f0e Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the
assembly text output uses an indirect call ("call *") instead of a direct call.

llvm-svn: 66735
2009-03-11 23:01:47 +00:00
Rafael Espindola
a8fe373200 optimize i8 and i16 tls values.
llvm-svn: 66725
2009-03-11 22:40:04 +00:00
Evan Cheng
042e05cb31 My last coalescer fix introduced a subtler one. It's aborting a commuting optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b.
llvm-svn: 66715
2009-03-11 22:18:44 +00:00
Mon P Wang
287e422039 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
llvm-svn: 66684
2009-03-11 18:47:57 +00:00
Chris Lattner
8fdb9ac396 implement support for C-style string literal concatenation in td files.
llvm-svn: 66663
2009-03-11 17:08:13 +00:00
Mon P Wang
2867737ad2 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
llvm-svn: 66645
2009-03-11 06:35:11 +00:00
Chris Lattner
a0c4a99ec2 reapply my previous patch (r66358) with a tweak to set the
alignment of the generated constant pool entry to the
desired alignment of a type.  If we don't do this, we end up
trying to do movsd from 4-byte alignment memory.  This fixes
450.soplex and 456.hmmer.

llvm-svn: 66641
2009-03-11 05:08:08 +00:00
Evan Cheng
264173da40 Two coalescer fixes in one.
1. Use the same value# to represent unknown values being merged into sub-registers.
2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges.

llvm-svn: 66610
2009-03-11 00:03:21 +00:00
Bill Wendling
5af061a657 Readd test, but XFAIL it.
llvm-svn: 66581
2009-03-10 21:31:00 +00:00
Evan Cheng
535dbf4ffd Revert 66358 for now. It's breaking povray, 450.soplex, and 456.hmmer on x86 / Darwin.
llvm-svn: 66574
2009-03-10 20:47:18 +00:00
Stuart Hastings
7a85288bc5 Tweak the DejaGNU voodoo to match Bill's advice.
llvm-svn: 66547
2009-03-10 16:44:45 +00:00
John Criswell
d1fd7b1f72 Do not attempt to do parial redundancy elimination on void values.
Also fixed a punctuation error in the header comment.
This fixes PR3775.

llvm-svn: 66542
2009-03-10 15:04:53 +00:00
Torok Edwin
3324e1f491 Global variables don't have a corresponding llvm.dbg.declare, yet it is possible
to obtain debug info about them.
Introduce helpers to access debug info for global variables. Also introduce a
helper that works for both local and global variables.

llvm-svn: 66541
2009-03-10 13:41:26 +00:00
Evan Cheng
c147115cdf If a function is marked alwaysinline, it must be inlined (possibly for correctness). Do so even if the callee has dynamic alloca and the caller doesn't.
llvm-svn: 66539
2009-03-10 07:57:50 +00:00
Bill Wendling
4ddb112b2f Add radar number.
llvm-svn: 66534
2009-03-10 06:53:54 +00:00
Chris Lattner
03060f6d50 wire up support for emitting "special" values from inline asm
format strings with the standard ${:foo} syntax.

llvm-svn: 66527
2009-03-10 05:37:13 +00:00
Stuart Hastings
cae607bb88 Check for warnings about inappropriate weak_imports.
Darwin-specific; marked XFAIL for others.

llvm-svn: 66514
2009-03-10 00:17:39 +00:00
Devang Patel
54b17d998a Ignore debug info while evaluating function.
llvm-svn: 66490
2009-03-09 23:04:12 +00:00
Chris Lattner
93662edfb8 Fix PR3763 by using proper APInt methods instead of uint64_t's.
llvm-svn: 66434
2009-03-09 20:22:18 +00:00
Evan Cheng
3c9a084a1b ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
llvm-svn: 66429
2009-03-09 19:15:00 +00:00
Evan Cheng
8b47b553f9 Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706.
llvm-svn: 66428
2009-03-09 19:00:05 +00:00
Chris Lattner
762ced6868 testcase for PR3744
llvm-svn: 66401
2009-03-09 05:44:59 +00:00
Chris Lattner
f05ebf0849 teach SROA to handle promoting vector allocas with a memset into them into
a vector type instead of into an integer type.

llvm-svn: 66368
2009-03-08 04:17:04 +00:00
Chris Lattner
54d2292fe5 Enhance SROA to "promote to scalar" allocas which are
memcpy/memmove'd into or out of.  This fixes a serious
perf issue that Nate ran into.

llvm-svn: 66366
2009-03-08 04:04:21 +00:00
Evan Cheng
67ccd79e39 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
llvm-svn: 66365
2009-03-08 04:02:49 +00:00
Evan Cheng
483ece4d2e If a MI uses the same register more than once, only mark one of them as 'kill'.
llvm-svn: 66363
2009-03-08 03:58:35 +00:00
Chris Lattner
578b634f56 implement an optimization to codegen c ? 1.0 : 2.0 as load { 2.0, 1.0 } + c*4.
For 2009-03-07-FPConstSelect.ll we now produce:

_f:
	xorl	%eax, %eax
	testl	%edi, %edi
	movl	$4, %ecx
	cmovne	%rax, %rcx
	leaq	LCPI1_0(%rip), %rax
	movss	(%rcx,%rax), %xmm0
	ret

previously we produced:

_f:
	subl	$4, %esp
	cmpl	$0, 8(%esp)
	movss	LCPI1_0, %xmm0
	je	LBB1_2	## entry
LBB1_1:	## entry
	movss	LCPI1_1, %xmm0
LBB1_2:	## entry
	movss	%xmm0, (%esp)
	flds	(%esp)
	addl	$4, %esp
	ret

on PPC the code also improves to:

_f:
	cntlzw r2, r3
	srwi r2, r2, 5
	li r3, lo16(LCPI1_0)
	slwi r2, r2, 2
	addis r3, r3, ha16(LCPI1_0)
	lfsx f1, r3, r2
	blr 

from:

_f:
	li r2, lo16(LCPI1_1)
	cmplwi cr0, r3, 0
	addis r2, r2, ha16(LCPI1_1)
	beq cr0, LBB1_2	; entry
LBB1_1:	; entry
	li r2, lo16(LCPI1_0)
	addis r2, r2, ha16(LCPI1_0)
LBB1_2:	; entry
	lfs f1, 0(r2)
	blr 

This also improves the existing pic-cpool case from:

foo:
	subl	$12, %esp
	call	.Lllvm$1.$piclabel
.Lllvm$1.$piclabel:
	popl	%eax
	addl	$_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$1.$piclabel], %eax
	cmpl	$0, 16(%esp)
	movsd	.LCPI1_0@GOTOFF(%eax), %xmm0
	je	.LBB1_2	# entry
.LBB1_1:	# entry
	movsd	.LCPI1_1@GOTOFF(%eax), %xmm0
.LBB1_2:	# entry
	movsd	%xmm0, (%esp)
	fldl	(%esp)
	addl	$12, %esp
	ret

to:

foo:
	call	.Lllvm$1.$piclabel
.Lllvm$1.$piclabel:
	popl	%eax
	addl	$_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$1.$piclabel], %eax
	xorl	%ecx, %ecx
	cmpl	$0, 4(%esp)
	movl	$8, %edx
	cmovne	%ecx, %edx
	fldl	.LCPI1_0@GOTOFF(%eax,%edx)
	ret

This triggers a few dozen times in spec FP 2000.

llvm-svn: 66358
2009-03-08 01:51:30 +00:00
Chris Lattner
fc43115972 fix a serious pessimization that Tron on IRC pointed out where we would
"boolify" pointers, generating really awful code because getting the pointer
value requires a load itself.  Before:

_foo:
	movb	$1, _X.b
	ret
_get:
	xorl	%ecx, %ecx
	movb	_X.b, %al
	testb	%al, %al
	movl	$_Y, %eax
	cmove	%ecx, %eax
	ret

With the xform disabled:

_foo:
	movl	$_Y, _X
	ret
_get:
	movl	_X, %eax
	ret

llvm-svn: 66351
2009-03-07 23:32:02 +00:00
Dan Gohman
b9c32f1aca Arithmetic instructions don't set EFLAGS bits OF and CF bits
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.

llvm-svn: 66318
2009-03-07 01:58:32 +00:00
Mikhail Glushenkov
f49e6643c9 Add a comment.
llvm-svn: 66278
2009-03-06 17:59:58 +00:00
Mikhail Glushenkov
5dadfaa7a0 Trailing whitespace.
llvm-svn: 66269
2009-03-06 12:25:56 +00:00
Mikhail Glushenkov
a2ea41c3a8 Trailing whitespace.
llvm-svn: 66268
2009-03-06 12:21:40 +00:00
Duncan Sands
26567dea82 While thinking about the one-definition-rule and trying
to find a tiny mouse hole to squeeze through, it struck
me that globals without a name can be considered internal
since they can't be referenced from outside the current
module.  This patch makes GlobalOpt give them internal
linkage.  Also done for aliases even though they always
have names, since in my opinion anonymous aliases should
be allowed for consistency with global variables and
functions.  So if that happens one day, this code is ready!

llvm-svn: 66267
2009-03-06 10:21:56 +00:00
Devang Patel
12e9aa7629 While converting an aggregate to scalare, ignore and remove aggregate's debug info.
llvm-svn: 66262
2009-03-06 07:03:54 +00:00
Devang Patel
3ae9d5d375 While hoisting instruction to speculatively execute simple bb, ignore dbg intrinsics.
llvm-svn: 66255
2009-03-06 06:00:17 +00:00
Devang Patel
9abfbc2e14 Skip DbgInfoIntrinsic.
llvm-svn: 66244
2009-03-06 02:59:27 +00:00