Craig Topper
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d5082631e1
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Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size.
llvm-svn: 192266
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2013-10-09 02:18:34 +00:00 |
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Benjamin Kramer
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a0c15494c5
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X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.
Give it the right register format so we can also emit it when AVX is enabled.
llvm-svn: 183971
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2013-06-14 09:31:41 +00:00 |
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Manman Ren
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584c3daf8d
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X86 MMX: optimize transfer from mmx to i32
We used to generate a store (movq) + a load.
Now we use movd.
rdar://9946746
llvm-svn: 167056
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2012-10-30 22:15:38 +00:00 |
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Craig Topper
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1fdcf7071d
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Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
llvm-svn: 147762
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2012-01-09 00:11:29 +00:00 |
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Bill Wendling
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4938e4d00a
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PSHUFW is in SSE, not SSSE3.
llvm-svn: 115691
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2010-10-05 21:58:12 +00:00 |
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Chris Lattner
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f58652610d
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unbreak buildbot
llvm-svn: 115476
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2010-10-03 20:02:48 +00:00 |
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Bill Wendling
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f1552256a1
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Add test to make sure that the MMX intrinsic calls make it out the other end in
tact.
llvm-svn: 115458
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2010-10-03 03:30:30 +00:00 |
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