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12394 Commits

Author SHA1 Message Date
Jim Grosbach
928cb87167 Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values. 
llvm-svn: 89618
 2009-11-22 20:05:32 +00:00
Jim Grosbach
33f06ed72e Generate more correct debug info for frame indices. 
llvm-svn: 89576
 2009-11-22 02:32:29 +00:00
Anton Korobeynikov
5511c0260f Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison. 
llvm-svn: 89574
 2009-11-22 01:14:08 +00:00
Anton Korobeynikov
10669b8c42 Drop unsupported imm operands 
llvm-svn: 89573
 2009-11-22 01:13:54 +00:00
Anton Korobeynikov
44886c9a90 Use 2-byte alignment for functions. 4 bytes are clear overkill here. 
llvm-svn: 89572
 2009-11-22 01:13:39 +00:00
Anton Korobeynikov
9cea2b264c Use semicolon as assembler comment string 
llvm-svn: 89571
 2009-11-22 01:12:49 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng
a7496ef9a6 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
llvm-svn: 89542
 2009-11-21 06:21:52 +00:00
Devang Patel
327919890c We are not using DBG_STOPPOINT anymore. 
llvm-svn: 89536
 2009-11-21 02:46:55 +00:00
Viktor Kutuzov
ac8f027245 Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. 
llvm-svn: 89516
 2009-11-21 00:00:02 +00:00
Dan Gohman
e5eddcd606 Fix a thinko that caused spurious @GOTOFFs. 
llvm-svn: 89509
 2009-11-20 23:30:32 +00:00
Dan Gohman
ca4026afec Update for new getBlockAddress signature. 
llvm-svn: 89507
 2009-11-20 23:21:00 +00:00
Dan Gohman
3517f425b8 Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
 2009-11-20 23:18:13 +00:00
Sean Callanan
78ee7f5d57 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Dale Johannesen
45f80d39f6 Remove an incorrect overaggressive optimization 
(PPC specific).

llvm-svn: 89496
 2009-11-20 22:16:40 +00:00
Sean Callanan
d92626fc0d Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan
0da77167d3 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Jim Grosbach
8371342c89 The verify() call of CPEIsInRange() isn't right for the assertion check of 
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473
 2009-11-20 19:37:38 +00:00
Jim Grosbach
0057f45c31 Remove verifySizes() since it's not adding much value. 
llvm-svn: 89443
 2009-11-20 02:32:06 +00:00
Evan Cheng
5fe8b0b3c5 Also CSE non-pic load from constant pools. 
llvm-svn: 89440
 2009-11-20 02:10:27 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Eric Christopher
fd3b2deb8f Update comment to reflect instruction. 
llvm-svn: 89414
 2009-11-20 00:21:55 +00:00
Jim Grosbach
9a19252df2 When placing constant islands and adjusting for alignment padding, inline 
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403
 2009-11-19 23:10:28 +00:00
Evan Cheng
af22254deb Refactor cmov selection code out to a separate function. No functionality change. 
llvm-svn: 89396
 2009-11-19 21:45:22 +00:00
Bill Wendling
fcbf6174ab Reverting the EH table patches. 
$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G    lib/CodeGen/AsmPrinter/DwarfException.cpp
G    lib/Target/TargetLoweringObjectFile.cpp

llvm-svn: 89379
 2009-11-19 19:21:09 +00:00
Johnny Chen
346e6b6cac Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not 
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377
 2009-11-19 19:20:17 +00:00
Jim Grosbach
75111632ca fix typo 
llvm-svn: 89369
 2009-11-19 18:23:19 +00:00
Dan Gohman
133120de6d Fix a typo in a comment. 
llvm-svn: 89360
 2009-11-19 16:35:11 +00:00
Evan Cheng
9730c9113e 80 col violation. 
llvm-svn: 89337
 2009-11-19 08:16:50 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
c2e359a418 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
llvm-svn: 89326
 2009-11-19 06:32:27 +00:00
Evan Cheng
aaccd1d07b Eliminate more * 4 in Thumb1 asm printing for consistency sake. 
llvm-svn: 89325
 2009-11-19 06:31:26 +00:00
Bruno Cardoso Lopes
bf95b9699e - Add sugregister logic to handle f64=(f32,f32). 
- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322
 2009-11-19 06:06:13 +00:00
Bruno Cardoso Lopes
2cb8938a96 Only use small sections for non linux targets! 
llvm-svn: 89316
 2009-11-19 05:28:18 +00:00
Bill Wendling
b396532e98 The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EH 
exception table than DataRel.

llvm-svn: 89279
 2009-11-19 00:09:14 +00:00
Richard Osborne
fc2d5141a4 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Bill Wendling
5ab3ea88a2 Attempt #2: 
Place the EH table in the __TEXT section on MachO. It saves space.

llvm-svn: 89270
 2009-11-18 23:18:46 +00:00
Viktor Kutuzov
036656936e Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple. 
llvm-svn: 89236
 2009-11-18 20:20:05 +00:00
David Goodwin
6b56e77397 Add ARMv6 itineraries. 
llvm-svn: 89218
 2009-11-18 18:39:57 +00:00
Bob Wilson
6993e5d049 Fix a few places that were missed when we converted to unified syntax. 
llvm-svn: 89214
 2009-11-18 18:10:35 +00:00
Bob Wilson
6b68bd153a Add a target hook to allow changing the tail duplication limit based on the 
contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187
 2009-11-18 03:34:27 +00:00
Bill Wendling
03a196010e The llvm-gcc front-end and the pass manager use two separate TargetData objects. 
This is probably not confined to *just* these two things.

Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).

After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.

Fix this by making the TD's structure type information an abstract type user.

llvm-svn: 89176
 2009-11-18 01:03:56 +00:00
Jim Grosbach
d4db2d58ae Enable arm jumpt table adjustment. 
llvm-svn: 89143
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov
f8557956d7 Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6 
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.

llvm-svn: 89137
 2009-11-17 20:04:59 +00:00
Johnny Chen
81b3815eb2 Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to 
distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108
 2009-11-17 17:17:50 +00:00
Evan Cheng
d7cf6167f1 Re-apply 89011. It's not to be blamed. 
llvm-svn: 89081
 2009-11-17 09:51:18 +00:00
Evan Cheng
52159ba00a Revert 89011. Buildbot thinks it might be breaking stuff. 
llvm-svn: 89076
 2009-11-17 09:20:28 +00:00
Jim Grosbach
7fc73a45da When moving a block for table jumps, make sure the prior block terminator 
is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022
 2009-11-17 01:21:04 +00:00