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938 Commits

Author SHA1 Message Date
Matt Arsenault
e19ddbd0dc R600: Mostly remove remaining AMDIL intrinsics. 
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
 2014-06-12 21:15:44 +00:00
Matt Arsenault
2c82883c7a R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
 2014-06-12 08:21:54 +00:00
Tom Stellard
28636a432f R600: Set correct InstrItinClass for instructions using *Helper classes 
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
 2014-06-11 20:51:42 +00:00
Tom Stellard
a92b046237 R600: BCNT_INT is a vector only instruction 
llvm-svn: 210702
 2014-06-11 20:51:39 +00:00
Matt Arsenault
b6b9bb5978 R600/SI: Fix bitcast between v2i32 and f64 
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
 2014-06-11 19:31:13 +00:00
Matt Arsenault
b8a7faa150 R600/SI: Update place using old subtarget predicate 
llvm-svn: 210683
 2014-06-11 18:11:34 +00:00
Matt Arsenault
33d239c3a3 R600/SI: Add common 64-bit LDS atomics 
llvm-svn: 210680
 2014-06-11 18:08:54 +00:00
Matt Arsenault
90d1f4fc84 R600/SI: Add instruction definitions for 64-bit LDS atomics 
llvm-svn: 210679
 2014-06-11 18:08:50 +00:00
Matt Arsenault
ffa54309ef R600/SI: Add 32-bit LDS atomic cmpxchg 
llvm-svn: 210678
 2014-06-11 18:08:48 +00:00
Matt Arsenault
5784f403fd R600/SI: Use LDS atomic inc / dec 
llvm-svn: 210677
 2014-06-11 18:08:45 +00:00
Matt Arsenault
3067074b27 R600/SI: Add other LDS atomic operations 
llvm-svn: 210676
 2014-06-11 18:08:42 +00:00
Matt Arsenault
c187b34585 R600/SI: Add instruction definitions for more LDS ops 
llvm-svn: 210675
 2014-06-11 18:08:39 +00:00
Matt Arsenault
e633c2eeb6 R600/SI: Fix backwards names for local atomic instructions. 
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
 2014-06-11 18:08:37 +00:00
Matt Arsenault
174782d2e9 R600/SI: Refactor local atomics. 
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
 2014-06-11 18:08:34 +00:00
Matt Arsenault
a75d166beb R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
 2014-06-11 17:50:44 +00:00
Matt Arsenault
52e8d9b98d R600/SI: Fix selection failure on scalar_to_vector 
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
 2014-06-11 17:40:32 +00:00
Rafael Espindola
40744fa427 Try to fix the msvc build. 
llvm-svn: 210636
 2014-06-11 04:41:37 +00:00
Matt Arsenault
3090d98faf Use cast instead of assert + dyn_cast 
llvm-svn: 210628
 2014-06-11 03:30:06 +00:00
Matt Arsenault
6728d3c17d R600: Add helper functions. 
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
 2014-06-11 03:29:54 +00:00
Tom Stellard
9f0e1d4d7f R600/SI: Emit an error when attempting to spill VGPRs v4 
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210588
 2014-06-10 21:20:41 +00:00
Tom Stellard
ba8f206726 R600/SI: Fix a crash when spilling SGPRs 
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210587
 2014-06-10 21:20:38 +00:00
Matt Arsenault
4f96643a42 R600: Use BCNT_INT for evergreen 
llvm-svn: 210569
 2014-06-10 19:18:28 +00:00
Matt Arsenault
6387e9a3dc R600/SI: Implement i64 ctpop 
llvm-svn: 210568
 2014-06-10 19:18:24 +00:00
Matt Arsenault
8407076508 R600/SI: Use bcnt instruction for ctpop 
llvm-svn: 210567
 2014-06-10 19:18:21 +00:00
Matt Arsenault
d30b483e1a R600: Handle fcopysign 
llvm-svn: 210564
 2014-06-10 19:00:20 +00:00
Matt Arsenault
5bfef73e00 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
llvm-svn: 210563
 2014-06-10 18:54:59 +00:00
Tom Stellard
aab1db4cd9 SelectionDAG: Expand SELECT_CC to SELECT + SETCC 
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

llvm-svn: 210539
 2014-06-10 16:01:22 +00:00
Matt Arsenault
f38f9f9399 R600/SI: Rename VOP3 helper class to be more general 
It has other uses besides shift instructions.

llvm-svn: 210478
 2014-06-09 17:00:46 +00:00
Matt Arsenault
c9f3bd4d6c R600/SI: Keep 64-bit not on SALU 
llvm-svn: 210476
 2014-06-09 16:36:31 +00:00
Matt Arsenault
a34a3c834c R600: Fix selection failure for vector bswap 
llvm-svn: 210475
 2014-06-09 16:20:25 +00:00
Matt Arsenault
9e400b2e26 R600/SI: Match rsq instructions 
llvm-svn: 210226
 2014-06-05 00:15:55 +00:00
Matt Arsenault
d9ef70c461 Use nullptr 
llvm-svn: 210222
 2014-06-05 00:01:12 +00:00
Matt Arsenault
ad098591b8 Fix typos 
llvm-svn: 210135
 2014-06-03 23:06:13 +00:00
Matt Arsenault
a36a2916ac R600: Set all float vector expands in the same place 
llvm-svn: 209988
 2014-06-01 07:38:21 +00:00
Matt Arsenault
1c23cf5566 R600/SI: Remove redundant patterns 
These patterns are already handled in the instruction definition.

llvm-svn: 209979
 2014-05-31 19:25:17 +00:00
Matt Arsenault
ff3cea9ab5 R600/SI: Fix [s|u]int_to_fp for i1 
llvm-svn: 209971
 2014-05-31 06:47:42 +00:00
Matt Arsenault
0f46ee15d3 R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

llvm-svn: 209787
 2014-05-29 01:18:01 +00:00
Matt Arsenault
7d507483f4 R600: Add definition for flat address space ID. 
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

llvm-svn: 209463
 2014-05-22 18:27:07 +00:00
Matt Arsenault
bfc007dbb5 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
 2014-05-22 18:09:12 +00:00
Matt Arsenault
90d0fd2ea0 R600: Add dag combine for BFE 
llvm-svn: 209461
 2014-05-22 18:09:07 +00:00
Matt Arsenault
4ab9246e99 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
llvm-svn: 209460
 2014-05-22 18:09:03 +00:00
Matt Arsenault
3728da5d51 R600: Implement computeMaskedBitsForTargetNode for BFE 
llvm-svn: 209459
 2014-05-22 18:09:00 +00:00
Matt Arsenault
c7d0679684 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault
fcb6cf68ee R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault
8c8ff09456 R600/SI: Move instruction pattern to instruction definition 
llvm-svn: 209454
 2014-05-22 17:45:20 +00:00
Matt Arsenault
cec6ae49e8 R600/SI: Match fp_to_uint / uint_to_fp for f64 
llvm-svn: 209388
 2014-05-22 03:20:30 +00:00
Matt Arsenault
8ec42a3269 R600: Add comment describing problems with LowerConstantInitializer 
llvm-svn: 209333
 2014-05-21 22:59:17 +00:00
Matt Arsenault
094f9f1e9c R600: Partially fix constant initializers for structs and vectors. 
This should extend the current workaround to work with structs
that only contain legal, scalar types.

llvm-svn: 209331
 2014-05-21 22:42:42 +00:00
Matt Arsenault
90ef7a5eaa Use cast<> instead of unchecked dyn_cast 
llvm-svn: 209310
 2014-05-21 18:03:59 +00:00