RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity
24,379 Commits 4 Branches 5 Tags 704 MiB
11e3cec8bd
Commit Graph

734 Commits

Author SHA1 Message Date
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Reid Spencer
b08854af39 Add the README files to the distribution. 
llvm-svn: 27651
 2006-04-13 06:39:24 +00:00
Nate Begeman
6cdc599d05 Disable switch lowering for targets based on the selection dag isel, 
letting the code generator handle them directly.

llvm-svn: 27539
 2006-04-08 19:46:55 +00:00
Jim Laskey
b93bc75add Foundation for call frame information. 
llvm-svn: 27491
 2006-04-07 16:34:46 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey
8688957c53 Translate llvm target registers to dwarf register numbers properly. 
llvm-svn: 27180
 2006-03-27 20:18:45 +00:00
Nate Begeman
3d518334b9 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156
 2006-03-27 01:32:24 +00:00
Chris Lattner
e199d55073 #include Intrinsics.h into all dag isels 
llvm-svn: 27109
 2006-03-25 06:47:10 +00:00
Jim Laskey
37a8c245ce D'oh - should be even numbered. 
llvm-svn: 27088
 2006-03-24 22:48:02 +00:00
Jim Laskey
1716e53341 Add dwarf register numbering to register data. 
llvm-svn: 27081
 2006-03-24 21:15:58 +00:00
Jim Laskey
cec9c18c62 Add support to locate local variables in frames (early version.) 
llvm-svn: 26994
 2006-03-23 18:12:57 +00:00
Chris Lattner
89e0790edb Eliminate IntrinsicLowering from TargetMachine. 
Make the CBE and V9 backends create their own, since they're the only ones that use it.

llvm-svn: 26974
 2006-03-23 05:43:16 +00:00
Nate Begeman
42736d46b2 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
 2006-03-17 01:40:33 +00:00
Chris Lattner
125881e75b Add support for 'special' llvm globals like debug info and static ctors/dtors. 
llvm-svn: 26628
 2006-03-09 06:14:35 +00:00
Chris Lattner
6b0947c277 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.

llvm-svn: 26541
 2006-03-05 05:08:37 +00:00
Chris Lattner
da5029790a Don't print constant initializers, they may span lines now. 
llvm-svn: 26403
 2006-02-27 20:09:23 +00:00
Chris Lattner
dfdfc6b22d The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter 
instructions are expensive.

llvm-svn: 26298
 2006-02-21 18:04:32 +00:00
Nate Begeman
9c0ab71f4a kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Nate Begeman
0bc71999b9 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Chris Lattner
e75debf037 Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires 
it, because this:

.bss
X:
.byte 0

results in the assembler warning: "initialization in bss segment".  Annoying.

llvm-svn: 26204
 2006-02-15 07:07:14 +00:00
Chris Lattner
8e7f48c96d Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc. 
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.

llvm-svn: 26202
 2006-02-15 06:41:34 +00:00
Chris Lattner
599b432345 Switch targets over to using SelectionDAG::getCALLSEQ_START to create 
CALLSEQ_START nodes.

llvm-svn: 26143
 2006-02-13 09:00:43 +00:00
Chris Lattner
f8458d73bb Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr 
intrinsics.

Autogen frameindex matcher

llvm-svn: 26107
 2006-02-10 07:35:42 +00:00
Chris Lattner
0dc11e140e Update to new-style flags usage, simplifying the .td file 
llvm-svn: 26106
 2006-02-10 06:58:25 +00:00
Chris Lattner
4e9d16a0ad Done 
llvm-svn: 26091
 2006-02-09 20:00:19 +00:00
Chris Lattner
5a10d24e67 Enable LSR by default for SPARC: it is a clear win. 
llvm-svn: 26090
 2006-02-09 19:59:55 +00:00
Evan Cheng
6bd0f9c4ba Match getTargetNode() changes (now return SDNode* instead of SDOperand). 
llvm-svn: 26085
 2006-02-09 07:17:49 +00:00
Chris Lattner
8eae5f68d5 add an option to turn on LSR. 
llvm-svn: 26080
 2006-02-09 05:06:36 +00:00
Chris Lattner
c81f375f21 Adjust to MachineConstantPool interface change: instead of keeping a 
value/alignment pair for each constant, keep a value/offset pair.

llvm-svn: 26078
 2006-02-09 04:46:04 +00:00
Evan Cheng
521e5a1bfe Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067
 2006-02-09 00:37:58 +00:00
Chris Lattner
c0012f8818 Fix the Sparc backend with Evan's recent tblgen changes 
llvm-svn: 26009
 2006-02-05 08:35:50 +00:00
Evan Cheng
973e4051d6 Use SelectRoot() as the entry to any tblgen based isel. 
llvm-svn: 25998
 2006-02-05 06:51:51 +00:00
Chris Lattner
1e16099e9f remove V8 reference 
llvm-svn: 25991
 2006-02-05 06:32:59 +00:00
Chris Lattner
834685ef3a Rename SPARC V8 target to be the LLVM SPARC target. 
llvm-svn: 25985
 2006-02-05 05:50:24 +00:00
Brian Gaeke
965df0b91b Great renaming: Sparc --> SparcV9 
llvm-svn: 11826
 2004-02-25 18:44:15 +00:00
Brian Gaeke
eae0364189 FunctionLiveVarInfo.h moved: include/llvm/CodeGen -> lib/Target/Sparc/LiveVar 
llvm-svn: 11804
 2004-02-24 19:46:00 +00:00
Alkis Evlogimenos
7f7d70a53c Move MOTy::UseType enum into MachineOperand. This eliminates the 
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715
 2004-02-22 19:23:26 +00:00
Chris Lattner
28131460da Adjustments to support the new ConstantAggregateZero class 
llvm-svn: 11474
 2004-02-15 05:55:15 +00:00
Alkis Evlogimenos
a31a767307 Use newly added next() and prior() utility functions. 
llvm-svn: 11430
 2004-02-14 01:18:34 +00:00
Alkis Evlogimenos
6d6ab846af Remove getAllocatedRegNum(). Use getReg() instead. 
llvm-svn: 11393
 2004-02-13 21:01:20 +00:00
Chris Lattner
da61b0ab20 Squish warning 
llvm-svn: 11375
 2004-02-13 16:14:50 +00:00
Brian Gaeke
7d1652ca5c Remove this MachineOpCodeFlags assertion - its test can never be false. 
llvm-svn: 11342
 2004-02-12 04:01:07 +00:00
Alkis Evlogimenos
b755d35fd2 Change MachineBasicBlock's vector of MachineInstr pointers into an 
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340
 2004-02-12 02:27:10 +00:00
Brian Gaeke
116a667130 MachineInstr::getOpCode() --> getOpcode() in SPARC back-end. 
llvm-svn: 11335
 2004-02-11 20:47:34 +00:00
Alkis Evlogimenos
fb5edb0b49 Increase constness. 
llvm-svn: 11322
 2004-02-11 17:55:09 +00:00
Alkis Evlogimenos
4b4342e865 Remove assert as the only integer registers on the sparc are physical. 
llvm-svn: 11317
 2004-02-11 06:04:51 +00:00
Alkis Evlogimenos
30c37082ae Fix previous broken commit. A MachineOperand may have opType == 
MO_VirtualRegister but if the register number is one of a physical
register is it considered as a physical register.

llvm-svn: 11315
 2004-02-11 05:55:00 +00:00
Alkis Evlogimenos
d2edafbc32 Remove assert as it is meaningless. MachineOperands can be tagged as 
MO_VirtualRegister but actually be representing a physical register.

llvm-svn: 11310
 2004-02-11 04:52:30 +00:00
Chris Lattner
d64519766e Stop using this method 
llvm-svn: 11282
 2004-02-10 21:12:06 +00:00
Chris Lattner
0d6d4075e3 Remvoe use of MO.isVirtualRegister(), turn an assertion into an assert() 
llvm-svn: 11280
 2004-02-10 20:47:24 +00:00