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Commit Graph

67154 Commits

Author SHA1 Message Date
NAKAMURA Takumi
122c55ae1d [CMake] Move intrinsics_gen to lib/Target out of add_public_tablegen_target.
add_public_tablegen_target is used somewhere.

llvm-svn: 201787
2014-02-20 13:42:30 +00:00
Benjamin Kramer
6492a4878f AsmParser: Disable Darwin-style macro argument expansion on non-darwin targets.
There is code in the wild that relies on $0 not being expanded.

llvm-svn: 201784
2014-02-20 13:36:32 +00:00
Daniel Sanders
742e6aefa1 [mips] Make mips64 the default CPU for the mips64 architecture
Summary:
This is consistent with the integrated assembler.
All mips64 codegen tests previously passed -mcpu. Removed -mcpu from
blez_bgez.ll and const-mult.ll to cover the default case.

Ideally, the two implementations of selectMipsCPU() will be merged but it's
proven difficult to find a home for the function that doesn't cause link errors.
For now, we'll hoist the common functionality into a function and mark it with
FIXME's.

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2830

llvm-svn: 201782
2014-02-20 13:13:33 +00:00
NAKAMURA Takumi
75450aa5ca COFFObjectFile.cpp: Appease msvc in r201760.
llvm-svn: 201769
2014-02-20 09:16:23 +00:00
Craig Topper
80c9d78b97 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
llvm-svn: 201767
2014-02-20 07:59:43 +00:00
Elena Demikhovsky
f4fb18943a AVX-512: Fixed compilation issue
llvm-svn: 201761
2014-02-20 07:00:10 +00:00
Rui Ueyama
c9f1e84a78 llvm-objdump/COFF: Print SEH table addresses.
SEH table addresses are VA in COFF file. In this patch we convert VA to RVA
before printing it, because dumpbin prints them as RVAs.

llvm-svn: 201760
2014-02-20 06:51:07 +00:00
Nick Lewycky
19e8384465 Fix change in behaviour accidentally introduced in r201754.
llvm-svn: 201758
2014-02-20 06:35:31 +00:00
Elena Demikhovsky
af8e1ef280 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.

llvm-svn: 201757
2014-02-20 06:34:39 +00:00
Nick Lewycky
d413ce9329 Simplify the implementation of getUnderlyingObjectsForInstr, without intending to change the semantics at all.
llvm-svn: 201754
2014-02-20 05:06:26 +00:00
Eric Christopher
eb6b7bc131 Add support for hashing attributes with DW_FORM_block. This required
passing down an AsmPrinter instance so we could compute the size of
the block which could be target specific. All of the test cases in
the unittest don't have any target specific data so we can use a NULL
AsmPrinter there. This also depends upon block data being added as
integers.

We can now hash the entire fission-cu.ll compile unit so turn the
flag on there with the hash value.

llvm-svn: 201752
2014-02-20 02:50:45 +00:00
Eric Christopher
690f652a2f Make DIELoc/DIEBlock's ComputeSize method const. Add a setSize
method to actually set it in the class to avoid computing it
multiple times.

llvm-svn: 201751
2014-02-20 02:40:45 +00:00
Eric Christopher
273c29a12d Format.
llvm-svn: 201750
2014-02-20 02:40:41 +00:00
Eric Christopher
043a17a7b0 Add support for hashing DW_FORM_sdata and a small testcase.
llvm-svn: 201747
2014-02-20 00:54:40 +00:00
Eric Christopher
750f6d6f17 Remove FIXME that had snuck in.
llvm-svn: 201745
2014-02-20 00:54:35 +00:00
Reed Kotler
325c6f3182 Make one statement easier to understand from post commmit feedback from a
review of the previous patch that introduced this week.

llvm-svn: 201723
2014-02-19 22:11:45 +00:00
Roman Divacky
1a91fd1bdc Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
llvm-svn: 201718
2014-02-19 21:35:39 +00:00
Rafael Espindola
60133f3afe move getNameWithPrefix and getSymbol to TargetMachine.
TargetLoweringBase is implemented in CodeGen, so before this patch we had
a dependency fom Target to CodeGen. This would show up as a link failure of
llvm-stress when building with -DBUILD_SHARED_LIBS=ON.

This fixes pr18900.

llvm-svn: 201711
2014-02-19 20:30:41 +00:00
Rafael Espindola
aea6192f20 Add back r201608, r201622, r201624 and r201625
r201608 made llvm corretly handle private globals with MachO. r201622 fixed
a bug in it and r201624 and r201625 were changes for using private linkage,
assuming that llvm would do the right thing.

They all got reverted because r201608 introduced a crash in LTO. This patch
includes a fix for that. The issue was that TargetLoweringObjectFile now has
to be initialized before we can mangle names of private globals. This is
trivially true during the normal codegen pipeline (the asm printer does it),
but LTO has to do it manually.

llvm-svn: 201700
2014-02-19 17:23:20 +00:00
Christian Pirker
1d938fb7c4 Test commit - remove the new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
llvm-svn: 201698
2014-02-19 16:58:28 +00:00
Daniel Sanders
b1311110b0 [mips] In the integrated assembler, select the default feature bits by changing the CPU value.
This is consistent with the way CodeGen acheives this. However, CodeGen
always selects mips32 (even when the architecture is mips64).

llvm-svn: 201694
2014-02-19 16:13:26 +00:00
Christian Pirker
be6d8a86fb Test commit - added a new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
llvm-svn: 201692
2014-02-19 16:07:32 +00:00
Daniel Sanders
a4b8f677a1 [mips] Use llvm::Triple in ParseMipsTriple() instead of manually parsing it
No functional change.

llvm-svn: 201689
2014-02-19 15:55:21 +00:00
Rafael Espindola
5bdf119d0c This reverts commit r201625 and r201624.
Since r201608 got reverted, it is not safe to use private linkage in these cases
until it is committed back.

llvm-svn: 201688
2014-02-19 15:49:46 +00:00
Daniel Sanders
a5d02b49e6 [mips] Remove unused NotN64 predicate
llvm-svn: 201682
2014-02-19 15:16:47 +00:00
Cameron McInally
7173a45caf Fix AVX512 vector sqrt assembly strings.
llvm-svn: 201681
2014-02-19 15:16:09 +00:00
Daniel Jasper
bf4e7d8ac3 Revert r201622 and r201608.
This causes the LLVMgold plugin to segfault. More information on the
replies to r201608.

llvm-svn: 201669
2014-02-19 12:26:01 +00:00
Tim Northover
1b102abe53 X86 CodeGenPrep: sink shufflevectors before shifts
On x86, shifting a vector by a scalar is significantly cheaper than shifting a
vector by another fully general vector. Unfortunately, because SelectionDAG
operates on just one basic block at a time, the shufflevector instruction that
reveals whether the right-hand side of a shift *is* really a scalar is often
not visible to CodeGen when it's needed.

This adds another handler to CodeGenPrepare, to sink any useful shufflevector
instructions down to the basic block where they're used, predicated on a target
hook (since on other architectures, doing so will often just introduce extra
real work).

rdar://problem/16063505

llvm-svn: 201655
2014-02-19 10:02:43 +00:00
Craig Topper
de3c74571e Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
llvm-svn: 201649
2014-02-19 08:25:02 +00:00
Craig Topper
b56c73e1c5 Reduce size of map field in X86 TSFlags since it now requires less bits.
llvm-svn: 201646
2014-02-19 07:29:07 +00:00
Craig Topper
7d159c5e98 Put some of the X86 formats in a more logical order.
llvm-svn: 201645
2014-02-19 06:59:13 +00:00
Craig Topper
5b20c52fcc Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
llvm-svn: 201641
2014-02-19 05:34:21 +00:00
Saleem Abdulrasool
27ee2a5853 MCAsmParser: support required parameters
This enhances the macro parser to parse and handle parameter qualifications,
which is needed to support required formal parameters in macro definitions.  A
required parameter may not be defaulted (though providing a default value is
accepted with a warning).  This improves GAS compatibility.

Partially addresses PR9248.

llvm-svn: 201630
2014-02-19 03:00:29 +00:00
Saleem Abdulrasool
1358c09cd6 MCAsmParser: change representation of MCAsmMacroParameter
Rather than using std::pair, create a structure to represent the type.  This is
a preliminary refactoring to enable required parameter handling.  Additional
state is needed to indicate required parameters.  This has a minor side effect
of improving readability by providing more accurate names compared to first and
second.

llvm-svn: 201629
2014-02-19 03:00:23 +00:00
Rafael Espindola
e5f011f1b1 Now that llvm always does the right thing with private, use it.
llvm-svn: 201625
2014-02-19 02:08:39 +00:00
Rafael Espindola
5381278d2b Avoid an infinite cycle with private linkage and -f{data|function}-sections.
When outputting an object we check its section to find its name, but when
looking for the section with -ffunction-section we look for the symbol name.

Break the loop by requesting a name with the private prefix when constructing
the section name. This matches the behavior before r201608.

llvm-svn: 201622
2014-02-19 01:28:30 +00:00
Rafael Espindola
d39a573c72 Fix PR18743.
The IR
@foo = private constant i32 42

is valid, but before this patch we would produce an invalid MachO from it. It
was invalid because it would use an L label in a section where the liker needs
the labels in order to atomize it.

One way of fixing it would be to just reject this IR in the backend, but that
would not be very front end friendly.

What this patch does is use an 'l' prefix in sections that we know the linker
requires symbols for atomizing them. This allows frontends to just use
private and not worry about which sections they go to or how the linker handles
them.

One small issue with this strategy is that now a symbol name depends on the
section, which is not available before codegen. This is not a problem in
practice. The reason is that it only happens with private linkage, which will
be ignored by the non codegen users (llvm-nm and llvm-ar).

llvm-svn: 201608
2014-02-18 22:24:57 +00:00
Rafael Espindola
c898de3245 Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.
This is quiet a bit less confusing now that TargetData was renamed DataLayout.

llvm-svn: 201606
2014-02-18 22:05:46 +00:00
Lang Hames
363c803d9a Consistently check 'IsCode' when allocating sections in RuntimeDyld (via
findOrEmitSection).

Vaidas Gasiunas's patch, r201259, fixed one instance where we were always
allocating sections as text. This patch fixes the remaining buggy call sites.

No test case: This isn't breaking anything that I know of, it's just
inconsistent.

<rdar://problem/15943542>

llvm-svn: 201605
2014-02-18 21:46:39 +00:00
Ana Pazos
9cdade7a3e [AArch64] Expanded sin, cos, pow with FP vector types inputs
llvm-svn: 201601
2014-02-18 20:31:05 +00:00
Rafael Espindola
d85e4eb0f5 Rename some member variables from TD to DL.
TargetData was renamed DataLayout back in r165242.

llvm-svn: 201581
2014-02-18 15:33:12 +00:00
Robert Lytton
3f025fc96b XCore target: Handle common linkage
llvm-svn: 201563
2014-02-18 11:21:59 +00:00
Robert Lytton
73848eb640 XCore target: addMemOperand as necessary
BuildMI instructions were not including MachineMemOperand information.
This was discovered by 'SingleSource/Benchmarks/Stanford/Oscar' failing
due to a FrameIndex load incorrectly being hoisted by postra-machine-licm.
No other tests have been found to fail.

llvm-svn: 201562
2014-02-18 11:21:53 +00:00
Robert Lytton
296ff43f53 XCore target: Fix llvm.eh.return and EH info register handling
llvm-svn: 201561
2014-02-18 11:21:48 +00:00
Tim Northover
83bbdcb246 GlobalMerge: move "-global-merge" option to the pass itself.
It's rather odd to have the flag enabling and disabling this pass only affect a
single target.

llvm-svn: 201559
2014-02-18 11:17:29 +00:00
Tim Northover
448249fd73 X86: use vpsllvd (& friends) for 16-bit shifts on Haswell
llvm-svn: 201558
2014-02-18 11:15:32 +00:00
Craig Topper
947a05e5c4 Add PS prefix to some classes I missed in r201538.
llvm-svn: 201551
2014-02-18 08:24:22 +00:00
Craig Topper
b5b81fb98b Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction.
llvm-svn: 201550
2014-02-18 08:18:29 +00:00
Elena Demikhovsky
8091d0ad88 AVX-512: Fixed size of mask registers
llvm-svn: 201546
2014-02-18 07:52:26 +00:00
Jiangning Liu
9508c695c8 Fix a typo about lowering AArch64 va_copy.
llvm-svn: 201541
2014-02-18 02:37:42 +00:00