1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Commit Graph

19 Commits

Author SHA1 Message Date
Evan Cheng
7b8f8c317e * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.

llvm-svn: 25154
2006-01-09 18:27:06 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
2005-12-26 09:11:45 +00:00
Evan Cheng
bd79f871a2 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
support which is fragile.
* Fixed a number of bugs.

llvm-svn: 24996
2005-12-23 22:11:47 +00:00
Evan Cheng
cf4f349880 * Commit the fix (by Chris) for a tblgen type inferencing bug.
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
2005-12-04 08:18:16 +00:00
Nate Begeman
b79a074c0a Nuke CodeGenInstruction's ValueType member, it is no longer used.
llvm-svn: 24556
2005-12-01 00:12:04 +00:00
Nate Begeman
3935bea6c1 fit into 80 columns
llvm-svn: 24554
2005-11-30 23:58:18 +00:00
Chris Lattner
a36ad00a9a Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
2005-11-19 07:05:57 +00:00
Chris Lattner
6c4ea26961 spell this variable right
llvm-svn: 23095
2005-08-26 20:42:52 +00:00
Chris Lattner
b474a0ab06 Expose a new flag to TargetInstrInfo
llvm-svn: 23094
2005-08-26 20:40:46 +00:00
Chris Lattner
36f99a1374 For now, just emit empty operand info structures.
llvm-svn: 22910
2005-08-19 16:57:28 +00:00
Chris Lattner
d03fa09ce7 Figure out how many operands each instruction has, keep track of whether
or not it's variable.

llvm-svn: 22885
2005-08-18 23:38:41 +00:00
Misha Brukman
960a8d47d7 Remove trailing whitespace
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
Chris Lattner
2aef5783b0 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
Nate Begeman
bbf7945b61 Add support for the isLoad and isStore flags, needed by the instruction scheduler
llvm-svn: 16554
2004-09-28 21:01:45 +00:00
Chris Lattner
7a941d7691 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
llvm-svn: 16553
2004-09-28 18:38:01 +00:00
Chris Lattner
d7240cdb18 Make the AsmWriter a first-class tblgen object. Allow targets to specify
name of the generated asmwriter class, and the name of the format string.

llvm-svn: 15747
2004-08-14 22:50:53 +00:00
Chris Lattner
a88aec6972 Start parsing more information from the Operand information
llvm-svn: 15644
2004-08-11 02:22:39 +00:00
Chris Lattner
350b76be29 Parse the operand list of the instruction. We currently support register and immediate operands.
llvm-svn: 15390
2004-08-01 07:42:39 +00:00
Chris Lattner
09d6e317a8 Add, and start using, the CodeGenInstruction class. This class represents
an instance of the Instruction tablegen class.

llvm-svn: 15385
2004-08-01 05:04:00 +00:00