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12538 Commits

Author SHA1 Message Date
Sanjiv Gupta
14c9f2ed42 Emit direction operand in binary insns that stores in memory. 
llvm-svn: 91777
 2009-12-19 13:52:01 +00:00
Nuno Lopes
78f040fa26 rename dprintf to dbgpritnf, in order to fix build with glibc (which already defines dprintf in stdio.h 
llvm-svn: 91775
 2009-12-19 12:07:00 +00:00
Sanjiv Gupta
65927cebf8 1. In indirect load/store insns , the name of fsr should be emitted as INDF. 
2. include standard asmbly headers in generated asmbly.

llvm-svn: 91768
 2009-12-19 08:26:25 +00:00
Douglas Gregor
f39dd74a3f Fix a bunch of little errors that Clang complains about when its being pedantic 
llvm-svn: 91764
 2009-12-19 07:05:23 +00:00
Daniel Dunbar
057ae7e82e Use memset instead of bzero, its more portable. 
llvm-svn: 91754
 2009-12-19 03:31:50 +00:00
Sean Callanan
18fa59f381 Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit 
incarnations), integrated into the MC framework.  

The disassembler is table-driven, using a custom TableGen backend to 
generate hierarchical tables optimized for fast decode.  The disassembler 
consumes MemoryObjects and produces arrays of MCInsts, adhering to the 
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).

The disassembler is documented in detail in

- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)

You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets.  Please let me know if you encounter any problems
with it.

llvm-svn: 91749
 2009-12-19 02:59:52 +00:00
Anton Korobeynikov
4e05e61a52 Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

llvm-svn: 91745
 2009-12-19 02:04:23 +00:00
Bill Wendling
aed33d79ab Changes from review: 
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
  doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.

llvm-svn: 91727
 2009-12-18 23:32:53 +00:00
Rafael Espindola
4f903d4548 Fix libstdc++ build on ARM linux and part of PR5770. 
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.

Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.

For a patch that make us detect problems like this earlier, take a look at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html

With that patch we assert as soon and the new instruction is added to the garbage set.

llvm-svn: 91691
 2009-12-18 16:59:39 +00:00
Tilmann Scheller
69e00966bb Fix wrong frame pointer save offset in the 64-bit PowerPC SVR4 ABI. 
Patch contributed by Ken Werner of IBM!

llvm-svn: 91681
 2009-12-18 13:00:34 +00:00
Tilmann Scheller
29361c46ac Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI. 
Patch contributed by Ken Werner of IBM!

llvm-svn: 91680
 2009-12-18 13:00:15 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Eric Christopher
0253008d0c Fix typo. 
llvm-svn: 91657
 2009-12-18 02:12:53 +00:00
Evan Cheng
a647318eb3 Re-apply 91623 now that I actually know what I was trying to do. 
llvm-svn: 91655
 2009-12-18 01:59:21 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
John McCall
923cb2d8d7 Pass the error string directly to llvm_unreachable instead of the residual 
(0 && "error").  Rough consensus seems to be that g++ *should* be diagnosing
this because the pointer makes it not an ICE in c++03.  Everyone agrees that
the current standard is silly and null-pointer-ness should not be based on
ICE-ness.  Excellent fight scene in Act II, denouement weak, two stars.

llvm-svn: 91644
 2009-12-18 00:27:18 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Jeffrey Yasskin
f39a138a7c Revert r91623 to unbreak the buildbots. 
llvm-svn: 91632
 2009-12-17 22:44:34 +00:00
Evan Cheng
d765952b17 Remove an unused option. 
llvm-svn: 91623
 2009-12-17 21:23:58 +00:00
Chris Lattner
b944c6eca5 finish cleaning up StructLayoutMap. 
llvm-svn: 91612
 2009-12-17 20:00:21 +00:00
Ken Dyck
319b2ed194 In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of 
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.

llvm-svn: 91602
 2009-12-17 15:31:52 +00:00
Johnny Chen
04b3259f9d Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
John McCall
8ee507f0f5 Silence a clang warning about the deprecated (but perfectly reasonable in 
context) increment-of-bool idiom.

llvm-svn: 91564
 2009-12-16 20:31:50 +00:00
Jim Grosbach
666c19db99 Mark STREX* as earlyclobber for the success result register. 
llvm-svn: 91555
 2009-12-16 19:44:06 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
John McCall
e3df19422d Every anonymous namespace is different. Caught by clang++. 
llvm-svn: 91481
 2009-12-16 00:15:28 +00:00
Jeffrey Yasskin
d50951dc1e Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464
 2009-12-15 22:42:46 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Evan Cheng
32946d6aae Fix an encoding bug. 
llvm-svn: 91417
 2009-12-15 06:49:02 +00:00
Kenneth Uildriks
c0ab5a6e88 For fastcc on x86, let ECX be used as a return register after EAX and EDX 
llvm-svn: 91410
 2009-12-15 03:27:52 +00:00
Evan Cheng
4adb4acc7b Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
llvm-svn: 91405
 2009-12-15 03:07:11 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Jim Grosbach
76d722dd6c nand atomic requires opposite operand ordering 
llvm-svn: 91371
 2009-12-15 00:12:35 +00:00
Dan Gohman
57dc006590 Fix integer cast code to handle vector types. 
llvm-svn: 91362
 2009-12-14 23:40:38 +00:00
Johnny Chen
61b6d221d2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

llvm-svn: 91339
 2009-12-14 21:51:34 +00:00
Jim Grosbach
dc0006c895 v6 sync insn copy/paste error 
llvm-svn: 91333
 2009-12-14 21:33:32 +00:00
Jim Grosbach
09167e5bbb Add ARMv6 memory and sync barrier instructions 
llvm-svn: 91329
 2009-12-14 21:24:16 +00:00
Johnny Chen
80b7b55eea Fixed encoding bits typo of ldrexd/strexd. 
llvm-svn: 91327
 2009-12-14 21:01:46 +00:00
Jim Grosbach
266c2d59e6 Thumb2 atomic operations 
llvm-svn: 91321
 2009-12-14 20:14:59 +00:00
Chris Lattner
81c6d73285 fix an obvious bug found by clang++ and collapse a redundant if. 
Here's the diagnostic from clang:

/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
        printConstant(gv);
                      ^
1 diagnostic generated.

llvm-svn: 91318
 2009-12-14 19:34:32 +00:00
Jim Grosbach
c7285dc721 correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
llvm-svn: 91313
 2009-12-14 19:24:11 +00:00
Jim Grosbach
723a7aa4e9 add Thumb2 atomic and memory barrier instruction definitions 
llvm-svn: 91310
 2009-12-14 18:56:47 +00:00
Jim Grosbach
99ace7c9ff whitespace 
llvm-svn: 91307
 2009-12-14 18:36:32 +00:00
Jim Grosbach
aaf39891f4 ARM memory barrier instructions are not predicable 
llvm-svn: 91305
 2009-12-14 18:31:20 +00:00
Jim Grosbach
5741d33c74 add ldrexd/strexd instructions 
llvm-svn: 91284
 2009-12-14 17:02:55 +00:00
Bill Wendling
e4328758f9 Whitespace changes, comment clarification. No functional changes. 
llvm-svn: 91274
 2009-12-14 06:51:19 +00:00
Jim Grosbach
87975f6229 atomic binary operations up to 32-bits wide. 
llvm-svn: 91260
 2009-12-14 04:22:04 +00:00
Anton Korobeynikov
fddfe4d096 Do not allow uninitialize access during debug printing 
llvm-svn: 91232
 2009-12-13 01:00:32 +00:00
Eli Friedman
392adbdd7d More info on this transformation. 
llvm-svn: 91230
 2009-12-12 23:23:43 +00:00