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32 Commits

Author SHA1 Message Date
Jim Grosbach
2c1ad70f1e Tidy up. 80 columns. 
llvm-svn: 151764
 2012-02-29 22:07:56 +00:00
James Molloy
85be8f7f88 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
llvm-svn: 150169
 2012-02-09 10:56:31 +00:00
Craig Topper
dfa8617ab9 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Owen Anderson
9e30a8355b Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions. 
llvm-svn: 142193
 2011-10-17 16:56:47 +00:00
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Bob Wilson
270da20c9e Subtarget getFeatureBits() returns a uint64_t, not unsigned. 
llvm-svn: 140928
 2011-10-01 02:47:54 +00:00
Eli Friedman
fd4451674b Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection. 
llvm-svn: 139317
 2011-09-08 21:00:31 +00:00
James Molloy
090d019a29 Fix warning on windows; use of comparison with bool argument. 
llvm-svn: 139286
 2011-09-08 08:12:01 +00:00
Andrew Trick
dc3f981b08 Fix a use of freed string contents. 
Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279
 2011-09-08 05:25:49 +00:00
Andrew Trick
daeb007cee whitespace 
llvm-svn: 139278
 2011-09-08 05:23:14 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Owen Anderson
3146968039 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Owen Anderson
c85618de24 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings. 
llvm-svn: 137171
 2011-08-09 23:05:23 +00:00
Owen Anderson
00a562a5c5 Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers. 
llvm-svn: 136660
 2011-08-01 22:45:43 +00:00
Owen Anderson
167040246a The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks. 
llvm-svn: 136645
 2011-08-01 20:06:49 +00:00
Owen Anderson
703d9b30bf Enhance the fixed length disassembler to better handle operand decoding failures. 
llvm-svn: 136635
 2011-08-01 18:44:37 +00:00
Owen Anderson
f946892d3e Correctly handle scattered operands where the bits of the operand are contiguous, but out of order. 
llvm-svn: 136534
 2011-07-29 23:01:18 +00:00
David Greene
43a26c71e8 Unconstify Inits 
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
 2011-07-29 22:43:06 +00:00
David Greene
b149019c5d [AVX] Constify Inits 
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
 2011-07-29 19:07:05 +00:00
Owen Anderson
b651954088 Third time's the charm for implementing tied operand decoding properly. 
llvm-svn: 136478
 2011-07-29 18:28:52 +00:00
Owen Anderson
b905884f67 Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping. 
llvm-svn: 136467
 2011-07-29 17:32:03 +00:00
Owen Anderson
8e67a44e7c Enhance the fixed-length decoder emitter to support tied operands. 
llvm-svn: 136431
 2011-07-28 23:56:20 +00:00
Owen Anderson
3650feb7f7 Enhance the fixed-length decoder emitter to support parsing scattered fields. 
llvm-svn: 136405
 2011-07-28 21:54:31 +00:00
Owen Anderson
ad0f17c102 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
llvm-svn: 135524
 2011-07-19 21:06:00 +00:00
Eric Christopher
3dd1f02420 Revert r134921, 134917, 134908 and 134907. They're causing failures 
in multiple buildbots.

llvm-svn: 134936
 2011-07-11 23:06:52 +00:00
David Greene
096bf5c02b [AVX] Make Inits Foldable 
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
 2011-07-11 18:25:51 +00:00
Jim Grosbach
68759971b3 Don't require pseudo-instructions to carry encoding information. 
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
 2011-07-06 21:33:38 +00:00
Owen Anderson
c1dcf312d1 Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. 
Patch by Jim Grosbach.

llvm-svn: 133940
 2011-06-27 21:06:21 +00:00
Owen Anderson
d98b684f30 Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly. 
llvm-svn: 129708
 2011-04-18 18:42:26 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Owen Anderson
49965661d5 Ignore isCodeGenOnly instructions when generating diassembly tables. 
llvm-svn: 127619
 2011-03-14 20:58:49 +00:00
Owen Anderson
a2d2de33c5 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings. 
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966
 2011-02-18 21:51:29 +00:00