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Commit Graph

21944 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
16126ffe0d Preserve operand flags in convertToThreeAddress() by copying operands.
No test case, this is a generalization of r160260.

llvm-svn: 162485
2012-08-23 22:36:31 +00:00
Craig Topper
3d4254e5b4 Favor FMA3 over FMA4 if both are enabled.
llvm-svn: 162454
2012-08-23 18:14:30 +00:00
Craig Topper
528004fc78 Use a switch statement instead of a bunch of if-else checks and pull out the common function call.
llvm-svn: 162428
2012-08-23 04:57:36 +00:00
Craig Topper
68f6b47a37 Remove unused private field to silence build warning.
llvm-svn: 162426
2012-08-23 04:45:31 +00:00
Akira Hatanaka
51dccb32d0 Make function loadImmediate a member of MipsSEInstrInfo and change it to return
the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use 
another register.

No changes in functionality.

llvm-svn: 162417
2012-08-23 00:21:05 +00:00
Akira Hatanaka
679d5c8fd7 Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class
Mips16RegisterInfo/MipsSERegisterInfo. 

No changes in functionality.

llvm-svn: 162413
2012-08-22 23:58:53 +00:00
Chad Rosier
437076336a [ms-inline asm] Avoid a false positive assertion
Assertion failed: (Start.isValid() == End.isValid() && "Start and end should 
either both be valid or both be invalid!")

when parsing inline asm.  SMLoc assumes that the first char * in the source is
invalid.  However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.

llvm-svn: 162381
2012-08-22 19:14:29 +00:00
Benjamin Kramer
e09e72a083 Reduce duplicated hash map lookups.
llvm-svn: 162362
2012-08-22 15:37:57 +00:00
Craig Topper
d66ff79b2c Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Craig Topper
ba3d5bef9f Don't cache the MBB in the class. Its only used by one function. Change a for loop over operands to use unsigned instead of int.
llvm-svn: 162344
2012-08-22 05:59:59 +00:00
Craig Topper
37bdfa3177 Mark a function as static since it doesn't use anything in the class.
llvm-svn: 162342
2012-08-22 05:36:44 +00:00
Akira Hatanaka
24b722f476 Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.

llvm-svn: 162340
2012-08-22 03:18:13 +00:00
Akira Hatanaka
0602c4e928 Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
default.

Patch by Carl Norum.

llvm-svn: 162339
2012-08-22 02:51:28 +00:00
Jack Carter
1b099ac7c7 For mips64 switch statements in subroutines could generate
within the codegen EK_GPRel64BlockAddress. This was not 
supported for direct object output and resulted in an assertion.

This change adds support for EK_GPRel64BlockAddress for 
direct object.

One fallout from this is to turn on rela relocations 
for mips64 to match gas.

llvm-svn: 162334
2012-08-22 00:49:30 +00:00
Chad Rosier
3f65a99bf7 Add a few functions to TargetLibraryInfo as part of PR13574.
Patch by Weiming Zhao <weimingz@codeaurora.org>.

llvm-svn: 162329
2012-08-21 23:28:56 +00:00
Richard Smith
d1addbb679 Fix unaligned memory accesses when performing relocations in X86 JIT. There's
no cost to using memcpy here: the fixed code is optimized by LLVM to perfect
machine code.

llvm-svn: 162311
2012-08-21 20:48:36 +00:00
Chad Rosier
92debd58d9 [ms-inline asm] Do not report a Parser error when matching inline assembly.
llvm-svn: 162306
2012-08-21 19:36:59 +00:00
Chad Rosier
72a2747c53 [ms-inline asm] Expose the ErrorInfo from the MatchInstructionImpl. In general,
this is the index of the operand that failed to match.

Note: This may cause a buildbot failure due to an API mismatch in clang.  Should
recover with my next commit to clang.

llvm-svn: 162295
2012-08-21 18:14:59 +00:00
Craig Topper
45eeb13dea Fix up indentation and remove a couple else's after returns.
llvm-svn: 162270
2012-08-21 08:29:51 +00:00
Craig Topper
aba5024223 Use uint16_t for tables of opcodes.
llvm-svn: 162267
2012-08-21 08:23:21 +00:00
Craig Topper
9831045ed8 Fix up indentation. No functional change.
llvm-svn: 162264
2012-08-21 08:17:07 +00:00
Craig Topper
63ef1d8341 Add a couple llvm_unreachables. Add a message to several others.
llvm-svn: 162263
2012-08-21 08:16:16 +00:00
Craig Topper
3ba0ae7ec3 Replace a break with llvm_unreachable in the default case of a nested switch. Condense code a bit. No functional change.
llvm-svn: 162261
2012-08-21 07:32:16 +00:00
Craig Topper
e432edabf1 Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms.
llvm-svn: 162260
2012-08-21 07:11:11 +00:00
Craig Topper
2e63b3ea18 Merge FMA3 instructions with and without patterns into single classes using null_frag.
llvm-svn: 162257
2012-08-21 05:56:45 +00:00
Jakob Stoklund Olesen
4403f82dbf Add a missing def flag.
*** Bad machine code: Explicit definition marked as use ***
- function:    test_cos
- basic block: BB#0 L.entry (0x7ff2a2024fd0)
- instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def>
- operand 0:   %D11

llvm-svn: 162247
2012-08-21 00:34:53 +00:00
Jakob Stoklund Olesen
4d875f1e57 Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.
The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating
duplicate successor list entries.

llvm-svn: 162222
2012-08-20 20:52:03 +00:00
Sebastian Pop
2f1237d5f4 fix HexagonSubtarget parsing of -mv flag
llvm-svn: 162217
2012-08-20 19:56:47 +00:00
Michael Liao
3d421a0c4d fix a case where all operands of BUILD_VECTOR are undefined
llvm-svn: 162214
2012-08-20 17:59:18 +00:00
Akira Hatanaka
b64681df6d Fix coding style violations in 162135 and 162136.
Patch by Petar Jovanovic.

llvm-svn: 162213
2012-08-20 17:53:24 +00:00
Craig Topper
77406bef3b Remove FMA3 intrinsic instructions in favor of patterns.
llvm-svn: 162194
2012-08-20 06:21:25 +00:00
Craig Topper
64c93f9d07 Use correct intrinsic for 256-bit VFMSUBADDPS.
llvm-svn: 162193
2012-08-20 06:03:04 +00:00
Craig Topper
832951e7da Remove trailing white space and tab characters. No functional change.
llvm-svn: 162192
2012-08-19 23:37:46 +00:00
Nadav Rotem
589dc766e0 When unsafe math is used, we can use commutative FMAX and FMIN. In some cases
this allows for better code generation.

Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.

For example:

  movaps  %xmm0, %xmm1
  movsd LC(%rip), %xmm0
  minsd %xmm1, %xmm0

becomes:

  minsd LC(%rip), %xmm0

llvm-svn: 162187
2012-08-19 13:06:16 +00:00
Benjamin Kramer
dca12ad159 Fabs folding is implemented.
llvm-svn: 162186
2012-08-19 09:51:44 +00:00
Jakob Stoklund Olesen
abf0a9ec82 Remove the CAND/COR/CXOR custom ISD nodes and their select code.
These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.

llvm-svn: 162179
2012-08-18 21:49:50 +00:00
Craig Topper
4362ba5082 Remove virtual from many methods. These methods replace methods in the base class, but the base class methods aren't virtual so it just increased call overhead.
llvm-svn: 162178
2012-08-18 21:38:45 +00:00
Jakob Stoklund Olesen
e78d4a5b08 Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:

  (add (zext cc), x) -> (select cc (add x, 1), x)
  (add (sext cc), x) -> (select cc (add x, -1), x)

For a function like:

  unsigned f(unsigned s, int x) {
    return s + (x>0);
  }

We now produce:

  cmp r1, #0
  it  gt
  addgt.w r0, r0, #1

Instead of:

  movs  r2, #0
  cmp r1, #0
  it  gt
  movgt r2, #1
  add r0, r2

llvm-svn: 162177
2012-08-18 21:25:22 +00:00
Jakob Stoklund Olesen
ece4a53017 Also pass logical ops to combineSelectAndUse.
Add these transformations to the existing add/sub ones:

  (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
  (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
  (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))

The selects can then be transformed to a single predicated instruction
by peephole.

This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.

llvm-svn: 162176
2012-08-18 21:25:16 +00:00
Nadav Rotem
d01a7b5942 Reapply r162160 with a fix: Optimize Arith->Trunc->SETCC sequence to allow better compare/branch code.
llvm-svn: 162172
2012-08-18 17:53:03 +00:00
Anton Korobeynikov
c0e610e681 fp16-to-fp32 conversion instructions are available in Thumb mode as well.
Make sure the generic pattern is used.

llvm-svn: 162170
2012-08-18 13:08:43 +00:00
Craig Topper
e341db552a Refactor code a bit to reduce number of calls in the final compiled code. No functional change intended.
llvm-svn: 162166
2012-08-18 06:39:34 +00:00
Craig Topper
d35582ae96 Reorder initialization list to silence -Wreorder
llvm-svn: 162165
2012-08-18 06:20:54 +00:00
Nadav Rotem
e9cdefa762 Revert r162160 because it made a few buildbots fail.
llvm-svn: 162164
2012-08-18 05:02:36 +00:00
Nadav Rotem
76f1b84f58 The X86 backend has a number of optimizations for SETCC nodes which use
arithmetic instructions. However, when small data types are used, a truncate
node appears between the SETCC node and the arithmetic operation. This patch
adds support for this pattern.

Before:
  xorl  %esi, %edi
  testb %dil, %dil
  setne %al
  ret

After:
  xorb  %dil, %sil
  setne %al
  ret

rdar://12081007

llvm-svn: 162160
2012-08-18 02:43:28 +00:00
Akira Hatanaka
ab6dca06f4 Add MipsELFWriterInfo.{h,cpp}.
llvm-svn: 162136
2012-08-17 21:38:47 +00:00
Akira Hatanaka
a50e7bd0a6 Correct MCJIT functionality for MIPS32 architecture.
No new tests are added.
All tests in ExecutionEngine/MCJIT that have been failing pass after this patch
is applied (when "make check" is done on a mips board). 

Patch by Petar Jovanovic.

llvm-svn: 162135
2012-08-17 21:28:04 +00:00
Jakob Stoklund Olesen
40eb30013e Avoid folding ADD instructions with FI operands.
PEI can't handle the pseudo-instructions. This can be removed when the
pseudo-instructions are replaced by normal predicated instructions.

Fixes PR13628.

llvm-svn: 162130
2012-08-17 20:55:34 +00:00
Akira Hatanaka
4e1b032521 Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.

llvm-svn: 162124
2012-08-17 20:16:42 +00:00
Bill Wendling
0569e9a6f3 Change the linker_private_weak_def_auto' linkage to linkonce_odr_auto_hide' to
make it more consistent with its intended semantics.

The `linker_private_weak_def_auto' linkage type was meant to automatically hide
globals which never had their addresses taken. It has nothing to do with the
`linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix
among other things.

The intended semantic is more like the `linkonce_odr' linkage type.

Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore
changing the semantics so that it produces the correct output for the linker.

Note: The old linkage name `linker_private_weak_def_auto' will still parse but
is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0.
<rdar://problem/11754934>

llvm-svn: 162114
2012-08-17 18:33:14 +00:00