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166cb23f62
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4638 Commits

Author SHA1 Message Date
Evan Cheng
166cb23f62 Fix spill weight updating bug. 
llvm-svn: 47507
 2008-02-23 00:33:04 +00:00
Evan Cheng
bb645b395c Same isPhysRegAvailable bug as local register allocator. 
llvm-svn: 47500
 2008-02-22 20:31:32 +00:00
Evan Cheng
b8e7eb2b1b Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when 
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

llvm-svn: 47499
 2008-02-22 20:30:53 +00:00
Evan Cheng
e24db258fe Add debugging printfs. 
llvm-svn: 47496
 2008-02-22 19:57:06 +00:00
Evan Cheng
fadafa2109 Make sure reload of implicit uses are issued before remat's. 
llvm-svn: 47492
 2008-02-22 19:22:06 +00:00
Dale Johannesen
a96eb3a1d8 Pass alignment on ByVal parameters, from FE, all 
the way through.  It is now used for codegen.

llvm-svn: 47484
 2008-02-22 17:49:45 +00:00
Evan Cheng
fa73e0c64e Enable re-materialization of instructions which have virtual register operands if 
the definition of the operand also reaches its uses.

llvm-svn: 47475
 2008-02-22 09:24:50 +00:00
Evan Cheng
e16e349623 Fix compiler warning. 
llvm-svn: 47468
 2008-02-22 01:48:00 +00:00
Dan Gohman
de80982418 Fix a regression in 403.gcc and 186.crafty introduced in 47383. To test 
that a value is >= 32, check that all of the high bits are zero, not
just one or more.

llvm-svn: 47467
 2008-02-22 01:12:31 +00:00
Chris Lattner
b3c8d120dc Make the clobber analysis a bit more smart: we only are careful about 
early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.

llvm-svn: 47457
 2008-02-21 20:54:31 +00:00
Chris Lattner
4f87f1c087 Treat clobber operands like early clobbers: if we have 
any, we force sdisel to do all regalloc for an asm.  This
leads to gross but correct codegen.

This fixes the rest of PR2078.

llvm-svn: 47454
 2008-02-21 19:43:13 +00:00
Bill Wendling
27dcf967b0 Clear PhysRegPartUse for the sub register as well. 
llvm-svn: 47453
 2008-02-21 19:35:27 +00:00
Bill Wendling
82f9e2d468 Adjust the MaxAlignment for the special register scavenging spill slot. 
llvm-svn: 47452
 2008-02-21 19:33:53 +00:00
Evan Cheng
8072166220 Help testing. 
llvm-svn: 47448
 2008-02-21 19:20:21 +00:00
Andrew Lenharth
b8f9871711 Better names as per Evan's request 
llvm-svn: 47435
 2008-02-21 16:11:38 +00:00
Andrew Lenharth
db9cd46f5d Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet 
llvm-svn: 47430
 2008-02-21 06:45:13 +00:00
Chris Lattner
702abbeb51 Add support for matching mem operands. This fixes PR1133, patch by 
Eli Friedman.  This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.

llvm-svn: 47428
 2008-02-21 05:27:19 +00:00
Chris Lattner
99b5a37d39 Fix a (harmless) but where vregs were added to the used reg lists for 
inline asms.

Fix PR2078 by marking aliases of registers used when a register is 
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.

llvm-svn: 47426
 2008-02-21 04:55:52 +00:00
Evan Cheng
f58113f597 Clean up some spilling code using MachineRegisterInfo. 
llvm-svn: 47416
 2008-02-21 00:34:19 +00:00
Bill Wendling
aaf11abe28 Remove one of the fixmes that I put in there. From Evan: 
No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).

llvm-svn: 47399
 2008-02-20 20:56:45 +00:00
Bill Wendling
df5f19c449 Improve some comments explaining the "handle kills" stuff better. 
llvm-svn: 47395
 2008-02-20 19:35:34 +00:00
Bill Wendling
753db180da Fix comment. 
llvm-svn: 47389
 2008-02-20 19:09:14 +00:00
Devang Patel
8a80334c8a assert is more effective reminder then FIXME tag for unimplemented features. 
llvm-svn: 47388
 2008-02-20 18:37:40 +00:00
Duncan Sands
86953f029f LegalizeTypes support for scalarizing a vector store 
and splitting extract_subvector.  This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.

llvm-svn: 47384
 2008-02-20 17:38:09 +00:00
Dan Gohman
149903436b Convert Legalize to use the APInt form of ComputeMaskedBits. 
llvm-svn: 47383
 2008-02-20 16:57:27 +00:00
Dan Gohman
48d03d5a2d Add explicit keywords. 
llvm-svn: 47382
 2008-02-20 16:44:09 +00:00
Dan Gohman
e83e624526 Convert DAGCombiner to use the APInt form of ComputeMaskedBits. 
llvm-svn: 47381
 2008-02-20 16:33:30 +00:00
Dan Gohman
e0923ed060 Use APInt::intersects. 
llvm-svn: 47380
 2008-02-20 16:30:17 +00:00
Anton Korobeynikov
c41f5b6af4 Fix newly-introduced 4.3 warnings 
llvm-svn: 47375
 2008-02-20 12:07:57 +00:00
Anton Korobeynikov
7dd00942cc Update gcc 4.3 warnings fix patch with recent head changes 
llvm-svn: 47368
 2008-02-20 11:10:28 +00:00
Anton Korobeynikov
0c5e186924 Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings. 
llvm-svn: 47367
 2008-02-20 11:08:44 +00:00
Bill Wendling
54bd12bc49 Added some comments and reformatted others. No functionality change. 
Added two "FIXMEs" for code that looks dubious to me (but I could be
wrong).

llvm-svn: 47366
 2008-02-20 09:15:16 +00:00
Bill Wendling
9a2a1ddf6e More constification of things. More comments added. No functionality 
changes. (Sorry for any formatting changes that creeped in.)

llvm-svn: 47362
 2008-02-20 07:36:31 +00:00
Chris Lattner
8705005be1 Fix an incredibly subtle bug exposed by Ted's change to APInt profiling. 
AddNodeIDNode does profiling for a ConstantSDNode, but so does 
SelectionDAG::getConstant.  This profiling should be moved to a common
static function in ConstantSDNode.

llvm-svn: 47359
 2008-02-20 06:28:01 +00:00
Bill Wendling
723b09a29d No functionality change: 
- Constified some MachineOperand values.
 - Added/Modified some comments.

llvm-svn: 47358
 2008-02-20 06:10:21 +00:00
Devang Patel
a74d2cbb6f Add GetResultInst. First step for multiple return value support. 
llvm-svn: 47348
 2008-02-19 22:15:16 +00:00
Evan Cheng
e18e5201fc PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB. 
llvm-svn: 47301
 2008-02-19 02:09:37 +00:00
Evan Cheng
bb577266bf - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type. 
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.

llvm-svn: 47290
 2008-02-18 23:04:32 +00:00
Evan Cheng
03fd8ea753 - Remove the previous check which broke coalescer-commute3.ll 
- For now, conservatively ignore copy MI whose source is a physical register. Commuting its def MI can cause a physical register live interval to be live through a loop (since we know it's live coming into the def MI).

llvm-svn: 47281
 2008-02-18 18:56:31 +00:00
Roman Levenstein
a7d4ae1435 New helper function getMBBFromIndex() that given an index in any instruction of an MBB returns a pointer the MBB. Reviewed by Evan. 
llvm-svn: 47267
 2008-02-18 09:35:30 +00:00
Evan Cheng
6eeae5bd62 For now, avoid commuting def MI for copy MI's whose source is not killed. That simply trade a live interval for another and because only the non-two-address operands can be folded into loads, may end up pessimising code. 
llvm-svn: 47262
 2008-02-18 08:40:53 +00:00
Andrew Lenharth
da54523742 I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. 
llvm-svn: 47213
 2008-02-16 14:46:26 +00:00
Duncan Sands
22ebf8b70f Teach LegalizeTypes how to expand the operands of 
br_cc.  This fixes 5 "make check" failures.

llvm-svn: 47212
 2008-02-16 10:29:26 +00:00
Evan Cheng
dd13a96a60 Refactor some code; check if commuteInstruction is able to commute the instruction. 
llvm-svn: 47208
 2008-02-16 02:32:17 +00:00
Andrew Lenharth
c178981b85 llvm.memory.barrier, and impl for x86 and alpha 
llvm-svn: 47204
 2008-02-16 01:24:58 +00:00
Bill Wendling
34dd48a10c Fix typos. 
llvm-svn: 47200
 2008-02-16 01:09:25 +00:00
Dan Gohman
a9386d8501 Rename CountMemOperands to ComputeMemOperandsEnd to reflect what 
it actually does. Simplify CountOperands a little by reusing
ComputeMemOperandsEnd. And reword some comments for both.

llvm-svn: 47198
 2008-02-16 00:36:48 +00:00
Dan Gohman
9ce252af04 Revert 47177, which was incorrect. 
llvm-svn: 47196
 2008-02-16 00:25:40 +00:00
Scott Michel
3ad0263173 Make tblgen a little smarter about constants smaller than i32. Currently, 
tblgen will complain if a sign-extended constant does not fit into a
data type smaller than i32, e.g., i16. This causes a problem when certain
hex constants are used, such as 0xff for byte masks or immediate xor
values.

tblgen will try the sign-extended value first and, if the sign extended
value would overflow, it tries to see if the unsigned value will fit.
Consequently, a software developer can now safely incant:

	(XORHIr16 R16C:$rA, 0xffff)

which is somewhat clearer and more informative than incanting:

	(XORHIr16 R16C:$rA, (i16 -1))

even if the two are bitwise equivalent.

Tblgen also outputs the 64-bit unsigned constant in the generated ISel code
when getTargetConstant() is invoked.

llvm-svn: 47188
 2008-02-15 23:05:48 +00:00
Evan Cheng
09fee0e727 The copy instruction being coalesced will be removed, it is not a kill. 
llvm-svn: 47179
 2008-02-15 21:36:51 +00:00