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378 Commits

Author SHA1 Message Date
Tom Stellard
7fed4dd0dd TargetLibraryInfo: Disable memcpy and memset on R600 
There are no implementations of these for R600.

llvm-svn: 205455
 2014-04-02 19:53:29 +00:00
Matt Arsenault
df61dc156f Fix missing RUN line in test 
llvm-svn: 205341
 2014-04-01 18:34:13 +00:00
Matt Arsenault
0062eb7871 Make isSetCCEquivalent respect the TargetBooleanContents 
llvm-svn: 205336
 2014-04-01 18:13:26 +00:00
Matt Arsenault
c36c1df67d R600: Compute masked bits for min and max 
llvm-svn: 205242
 2014-03-31 19:35:33 +00:00
Matt Arsenault
0d30a17857 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 
llvm-svn: 205236
 2014-03-31 18:21:18 +00:00
Tom Stellard
c6c05561d5 R600/SI: Lower i64 SELECT by bitcasting to a vector type 
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.

llvm-svn: 205187
 2014-03-31 14:01:55 +00:00
Matt Arsenault
7f99777a74 R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

llvm-svn: 204946
 2014-03-27 17:23:31 +00:00
Matt Arsenault
e42a0c31f3 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
llvm-svn: 204945
 2014-03-27 17:23:24 +00:00
Matt Arsenault
97718f1b49 R600: Add a testcase for sext_in_reg I missed. 
This sext_inreg i32 in i64 case was already handled, but not enabled.

llvm-svn: 204840
 2014-03-26 18:31:06 +00:00
Matt Arsenault
a88c889ce0 R600: Add failing testcase for <3 x i32> stores. 
This is supposed to have the same store size and alignment as <4 x i32>,
but currently is split into a 64-bit and 32-bit store.

llvm-svn: 204729
 2014-03-25 16:50:55 +00:00
Matt Arsenault
94cdf74a4b R600/SI: Fix extra mov from legalizing 64-bit SALU ops. 
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

llvm-svn: 204662
 2014-03-24 20:08:13 +00:00
Matt Arsenault
3436234471 R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops. 
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

llvm-svn: 204661
 2014-03-24 20:08:09 +00:00
Matt Arsenault
ed12a24627 R600/SI: Fix 64-bit bit ops that require the VALU. 
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

llvm-svn: 204660
 2014-03-24 20:08:05 +00:00
Matt Arsenault
7ae7f52221 R600: Implement isNarrowingProfitable. 
llvm-svn: 204658
 2014-03-24 19:43:31 +00:00
Matt Arsenault
e063f39ed3 R600/SI: Fix 64-bit private loads. 
llvm-svn: 204630
 2014-03-24 17:50:46 +00:00
Matt Arsenault
f0af6362fd R600/SI: Move instruction patterns to scalar versions. 
Some of them also had the pattern on both, so this removes the
duplication.

llvm-svn: 204492
 2014-03-21 18:01:18 +00:00
Tom Stellard
e5e3293278 R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 
llvm-svn: 204476
 2014-03-21 15:51:57 +00:00
Tom Stellard
8078855521 R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU() 
llvm-svn: 204475
 2014-03-21 15:51:54 +00:00
Matt Arsenault
a604a1a412 R600/SI: Add support for 64-bit LDS writes 
llvm-svn: 204274
 2014-03-19 22:19:54 +00:00
Matt Arsenault
35f86bd433 R600/SI: Add support for 64-bit LDS loads. 
v2:
  -Use correct opcode for DS_READ_64

llvm-svn: 204273
 2014-03-19 22:19:52 +00:00
Matt Arsenault
38344ebbaf R600/SI: Match i16 immediate offset of LDS instructions. 
llvm-svn: 204272
 2014-03-19 22:19:49 +00:00
Matt Arsenault
194b9e9539 R600/SI: Fix test checking wrong instruction operand. 
The source and destination happen to be the same register.

llvm-svn: 204271
 2014-03-19 22:19:45 +00:00
Matt Arsenault
45311f1864 R600/SI: Don't display the GDS bit. 
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

llvm-svn: 204270
 2014-03-19 22:19:43 +00:00
NAKAMURA Takumi
a0deabb112 CodeGen/R600/v_cndmask.ll: Relax an expression to unbreak msvcrt. 
V_CNDMASK_B32_e64 v0, v0, -1.#QNAN0e+00, s[2:3], 0, 0, 0, 0

FIXME: We really need to implement our formatter...
llvm-svn: 204118
 2014-03-18 06:17:22 +00:00
Kevin Enderby
b8221f3c03 Making a guess to fix the test case with r204056 to get the build bot working. 
llvm-svn: 204073
 2014-03-17 19:00:03 +00:00
Matt Arsenault
553297669c R600: Match sign_extend_inreg to BFE instructions 
llvm-svn: 204072
 2014-03-17 18:58:11 +00:00
Tom Stellard
6f60ceca31 R600/SI: Fix implementation of isInlineConstant() used by the verifier 
The type of the immediates should not matter as long as the encoding is
equivalent to the encoding of one of the legal inline constants.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 204056
 2014-03-17 17:03:52 +00:00
Tom Stellard
6b4e505e41 R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 
This instructions writes to an 32-bit SGPR.  This change required adding
the 32-bit VCC_LO and VCC_HI registers, because the full VCC register
is 64 bits.

This fixes verifier errors on several of the indirect addressing piglit
tests.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 204055
 2014-03-17 17:03:51 +00:00
Tom Stellard
c33b600343 R600: LDS instructions shouldn't implicitly define OQAP 
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

llvm-svn: 203818
 2014-03-13 17:13:04 +00:00
Matt Arsenault
469ede65b2 R600: Fix trunc store from i64 to i1 
llvm-svn: 203695
 2014-03-12 18:45:52 +00:00
Tom Stellard
bee4678d48 R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 203281
 2014-03-07 20:12:39 +00:00
Tom Stellard
230af572ff R600/SI: Custom lower i1 stores 
These are sometimes created by the shrink to boolean optimization in the
globalopt pass.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 203280
 2014-03-07 20:12:33 +00:00
Matt Arsenault
8140d7d370 R600: Fix extloads from i8 / i16 to i64. 
This appears to only be working for global loads. Private
and local break for other reasons.

llvm-svn: 203135
 2014-03-06 17:34:12 +00:00
Matt Arsenault
f68a94e609 R600/SI: Expand selects on vectors. 
llvm-svn: 203134
 2014-03-06 17:34:03 +00:00
Matt Arsenault
394a9d104d R600: Add failing control flow tests. 
Simple cases hit a variety of problems at -O0.

llvm-svn: 202601
 2014-03-01 21:45:41 +00:00
Tom Stellard
6280afdecd R600/SI: Expand all v16[if]32 operations 
llvm-svn: 202543
 2014-02-28 21:36:37 +00:00
Michel Danzer
8edacce1de R600/SI: Optimize SI_KILL for constant operands 
If the SI_KILL operand is constant, we can either clear the exec mask if
the operand is negative, or do nothing otherwise.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 202337
 2014-02-27 01:47:09 +00:00
Michel Danzer
0ddce64f7c R600/SI: Allow SI_KILL for geometry shaders 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 202336
 2014-02-27 01:47:02 +00:00
Tom Stellard
3dafad8efc R600/SI: Custom select 64-bit ADD 
llvm-svn: 202194
 2014-02-25 21:36:18 +00:00
Matt Arsenault
a3de4dc001 R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

llvm-svn: 202077
 2014-02-24 21:01:28 +00:00
Quentin Colombet
5c6ea83f97 [CodeGenPrepare] Fix the check of the legality of an instruction. 
The API expects an ISD opcode, not an IR opcode.
Fixes a regression for R600.

Related to <rdar://problem/15519855>.

llvm-svn: 201923
 2014-02-22 01:06:41 +00:00
Nico Rieck
f3b62a4af6 Fix more broken CHECK lines 
llvm-svn: 201493
 2014-02-16 13:28:39 +00:00
Quentin Colombet
5700bbac29 [CodeGenPrepare][AddressingModeMatcher] Give up on type promotion if the 
transformation does not bring any immediate benefits and introduce an illegal
operation. 

llvm-svn: 201439
 2014-02-14 22:23:22 +00:00
Tom Stellard
a3a801780f TargetLowering: n * r where n > 2 should be an illegal addressing mode 
llvm-svn: 201433
 2014-02-14 21:10:34 +00:00
Tom Stellard
988925aeae R600/SI: Expand all v8[if]32 operations 
llvm-svn: 201371
 2014-02-13 23:34:15 +00:00
Tom Stellard
309a624102 R600/SI: Add a pattern for i32 anyext 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 201370
 2014-02-13 23:34:13 +00:00
Tom Stellard
4b0c3551df R600/SI: Completely Disable TypeRewriter on compute 
llvm-svn: 201369
 2014-02-13 23:34:12 +00:00
Tom Stellard
4447febe55 R600/SI: Split global vector loads with more than 4 elements 
llvm-svn: 201368
 2014-02-13 23:34:10 +00:00
Tom Stellard
de306d4a6d R600/SI: Add ShaderType attribute to some tests 
llvm-svn: 201367
 2014-02-13 23:34:07 +00:00
Matt Arsenault
cc13cc04ab R600/SI: Fix assertion on infinite loops. 
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

llvm-svn: 201177
 2014-02-11 21:12:38 +00:00