Bill Wendling
7121342ad5
Reapply r141365 now that PR11107 is fixed.
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llvm-svn: 141591
2011-10-10 22:59:55 +00:00
Bill Wendling
7cba44defc
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
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hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
Anton Korobeynikov
0944a4c5cc
Peephole optimization for ABS on ARM.
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Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
Kevin Enderby
5a09a8db55
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
Jim Grosbach
c7a9669343
Thumb2 ADD/SUB can take SP as a destination register.
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It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
James Molloy
c4fcff419c
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
Jim Grosbach
b503a2183e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
Owen Anderson
79c9401e0e
Remove extraneous commit garbage.
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llvm-svn: 140581
2011-09-26 23:14:02 +00:00
Owen Anderson
7742c81cde
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
Owen Anderson
e63c963148
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
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llvm-svn: 140422
2011-09-23 21:57:50 +00:00
Owen Anderson
53c6b08ad8
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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llvm-svn: 140420
2011-09-23 21:26:40 +00:00
Owen Anderson
22ab29756b
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
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llvm-svn: 140284
2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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llvm-svn: 140283
2011-09-21 23:44:46 +00:00
Andrew Trick
c94573ded6
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
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This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
Andrew Trick
bfac89c238
Restore hasPostISelHook tblgen flag.
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No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick
53aeb9f663
ARM isel bug fix for adds/subs operands.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Jim Grosbach
e936bdc286
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
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llvm-svn: 140125
2011-09-20 00:46:54 +00:00
Jim Grosbach
882f1ec6d5
Remove incorrect comments. These are not disassmebly only patterns.
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llvm-svn: 140116
2011-09-20 00:26:34 +00:00
Jim Grosbach
794028c0e0
Thumb2 range check on CPS mode immediate.
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llvm-svn: 140105
2011-09-19 23:58:31 +00:00
Jim Grosbach
011bd172ea
Tidy up comments.
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llvm-svn: 140099
2011-09-19 23:38:34 +00:00
Jim Grosbach
6da9e6b23d
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
Jim Grosbach
207a337a60
Tidy up a bit.
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llvm-svn: 140050
2011-09-19 20:31:59 +00:00
Jim Grosbach
c7fa5f0c00
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
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llvm-svn: 140047
2011-09-19 20:29:33 +00:00
Owen Anderson
4bf9e290e9
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
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llvm-svn: 140041
2011-09-19 20:00:02 +00:00
Jim Grosbach
c677995374
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
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llvm-svn: 140029
2011-09-19 17:56:37 +00:00
Jim Grosbach
95242bff08
Thumb2 assembly parsing and encoding for SUB(immediate).
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llvm-svn: 139966
2011-09-16 22:58:42 +00:00
Owen Anderson
3a487c8c9b
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
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llvm-svn: 139958
2011-09-16 22:17:02 +00:00
Jim Grosbach
d521731d40
Thumb2 assembly parsing and encoding for STR.
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More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
Jim Grosbach
371c88528b
Tidy up. 80 columns.
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llvm-svn: 139944
2011-09-16 21:09:00 +00:00
Jim Grosbach
916a6c71aa
Thumb2 assembly parsing and encoding for STR(immediate).
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Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
Jim Grosbach
13af7198d5
Thumb2 assembly parsing and encoding for STMIA.
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llvm-svn: 139938
2011-09-16 20:50:13 +00:00
Jim Grosbach
6f6453f64b
Thumb2 assembly parsing and encoding for SSAT.
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llvm-svn: 139926
2011-09-16 18:32:30 +00:00
Jim Grosbach
5a8b63fe51
Thumb2 assembly parsing and encoding for SRS.
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llvm-svn: 139925
2011-09-16 18:25:22 +00:00
Jim Grosbach
3c3a9393ab
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
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llvm-svn: 139909
2011-09-16 17:10:44 +00:00
Jim Grosbach
9e471afd9c
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
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llvm-svn: 139906
2011-09-16 16:58:03 +00:00
Jim Grosbach
27a086b1d0
Remove incorrect comments.
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llvm-svn: 139877
2011-09-15 23:45:50 +00:00
Jim Grosbach
553692fcce
Thumb2 assembly parsing and encoding for RSB.
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llvm-svn: 139839
2011-09-15 20:54:14 +00:00
Jim Grosbach
50ee930e9a
Thumb2 assembly parsing and encoding for REV16/REVSH.
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llvm-svn: 139828
2011-09-15 19:46:13 +00:00
Jim Grosbach
9d7aa9bcbc
Thumb2 assembly parsing and encoding for REV.
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llvm-svn: 139813
2011-09-15 18:13:30 +00:00
Jim Grosbach
d428c970e3
Thumb2 push/pop mnemonic recognition.
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llvm-svn: 139794
2011-09-15 15:55:04 +00:00
Jim Grosbach
669e269758
Thumb2 assembly parsing and encoding for PKH.
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llvm-svn: 139754
2011-09-14 23:16:41 +00:00
Jim Grosbach
e841adae12
Thumb2 assembly parsing and encoding for MVN.
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llvm-svn: 139739
2011-09-14 21:24:41 +00:00
Jim Grosbach
b1c70aab3e
Thumb2 assembly parsing and encoding for MSR/MRS.
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Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
Owen Anderson
d0121fe635
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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llvm-svn: 139639
2011-09-13 20:46:26 +00:00
Eli Friedman
c6ff621dc5
Zap some junk from the ARM instruction descriptions.
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llvm-svn: 139575
2011-09-13 02:29:58 +00:00
Owen Anderson
a1a10ed5c6
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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llvm-svn: 139542
2011-09-12 21:28:46 +00:00
Jim Grosbach
52492b1cf3
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
Owen Anderson
dbe77fc5a1
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
Owen Anderson
a7838cb723
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Jim Grosbach
915ba5189e
Thumb2 assembly parsing and encoding for LDRSB.
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llvm-svn: 139389
2011-09-09 19:42:40 +00:00