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Author SHA1 Message Date
Eli Friedman
5927cb56e3 First draft of the practical guide to atomics. 
This is mostly descriptive of the intended state once atomic load and store have landed.  

llvm-svn: 137145
 2011-08-09 21:07:10 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Bob Wilson
1ac635c712 Put Darwin-specific code inside an __APPLE__ ifdef. 
llvm-svn: 137137
 2011-08-09 19:54:32 +00:00
Bill Wendling
250ea7930e Revert r137134. It breaks some code as Eli pointed out. 
llvm-svn: 137135
 2011-08-09 18:56:35 +00:00
Bill Wendling
ca256c0d2d Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081

llvm-svn: 137134
 2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen
e43aca1c39 Inflate register classes after coalescing. 
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

llvm-svn: 137133
 2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes
633400ee00 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

llvm-svn: 137128
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
1962a341d8 Revert r137114 
llvm-svn: 137127
 2011-08-09 17:39:01 +00:00
Justin Holewinski
021ab783b7 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

llvm-svn: 137125
 2011-08-09 17:36:31 +00:00
Jakob Stoklund Olesen
cbd8bcf3b8 Move CalculateRegClass to MRI::recomputeRegClass. 
This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.

llvm-svn: 137123
 2011-08-09 16:46:27 +00:00
Renato Golin
dc14179294 Emitting ARM build attributes and values as ULEB, rather than char. 
llvm-svn: 137115
 2011-08-09 09:50:10 +00:00
Bruno Cardoso Lopes
5dac86dac6 Handle sitofp between v4f64 <- v4i32. Fix PR10559 
llvm-svn: 137114
 2011-08-09 05:48:01 +00:00
Bob Wilson
a97bb9535d Recognize the UNAME_RELEASE environment variable to match Darwin's uname. 
When this variable is set, "uname -r" will return its value instead of the
real OS version.  Make this affect LLVM's triple for consistency.
<rdar://problem/9919167>

llvm-svn: 137111
 2011-08-09 05:13:36 +00:00
Andrew Trick
b9ef7f9e3e LoopUnroll looks like it has some stale code. Remove it to prove my sanity and avoid further confusion. 
llvm-svn: 137106
 2011-08-09 03:11:29 +00:00
Bruno Cardoso Lopes
d521431558 Add support for avx vector fextend 
llvm-svn: 137105
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
09a727298f Add AVX versions of 128-bit sitofp and fptosi 
llvm-svn: 137104
 2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
81534df169 Rename and tidy up tests 
llvm-svn: 137103
 2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes
1025d1eb3b Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

llvm-svn: 137100
 2011-08-09 01:43:09 +00:00
Bill Wendling
e3f1ab16df There is only one instance of this placeholder being created. Just use that 
instead of a vector.

llvm-svn: 137099
 2011-08-09 01:17:10 +00:00
Bill Wendling
23cae0966d Remove an instance where the 'unwind' instruction was created. 
The 'unwind' instruction was acting essentially as a placeholder, because it
would be replaced at the end of this function by a branch to the "unwind
handler". The 'unwind' instruction is going away, so use 'unreachable' instead,
which serves the same purpose as a placeholder.

llvm-svn: 137098
 2011-08-09 01:09:21 +00:00
Devang Patel
4e5d42a98e Print variable's inline location in debug output. 
llvm-svn: 137096
 2011-08-09 01:03:35 +00:00
Devang Patel
1d038e6e01 Provide method to print variable's extended name which includes inline location. 
llvm-svn: 137095
 2011-08-09 01:03:14 +00:00
Jakob Stoklund Olesen
4872d9f414 Rename member variables to follow coding standards. 
No functional change.

llvm-svn: 137094
 2011-08-09 01:01:27 +00:00
Bill Wendling
0359c2012c Add missing attributes to the C++ backend's output. 
llvm-svn: 137091
 2011-08-09 00:47:30 +00:00
Bruno Cardoso Lopes
d7eac41193 Make LowerVSETCC aware of AVX types and add patterns to match them. 
llvm-svn: 137090
 2011-08-09 00:46:57 +00:00
Jakob Stoklund Olesen
ef49b7bc1a Move the RegisterCoalescer private to its implementation file. 
RegisterCoalescer.h still has the CoalescerPair class interface.

llvm-svn: 137088
 2011-08-09 00:43:37 +00:00
Dan Gohman
a716e5c67e Tidy up these testcases to look more like real code does. 
llvm-svn: 137085
 2011-08-09 00:33:11 +00:00
Jakob Stoklund Olesen
2f58336f2f Refer to the RegisterCoalescer pass by ID. 
A public interface is no longer needed since RegisterCoalescer is not an
analysis any more.

llvm-svn: 137082
 2011-08-09 00:29:53 +00:00
Jim Grosbach
d6da18cf19 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Owen Anderson
5b0611a4eb Thumb1 BL instructions encoding 22 bits of displacement, not 21. 
llvm-svn: 137073
 2011-08-08 23:25:22 +00:00
Bill Wendling
8fb8ed6fc8 Indicate that there are changes if runOfFunction returns saying that there are. 
Patch by Jingyue!

llvm-svn: 137072
 2011-08-08 23:01:10 +00:00
Jim Grosbach
dce26073db ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach
1dbe50798e Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Jakob Stoklund Olesen
c239010f17 Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM. 
They improve the verbose assembly.

llvm-svn: 137069
 2011-08-08 21:45:32 +00:00
Bruno Cardoso Lopes
d8534855ff Add support for several vector shifts operations while in AVX mode. Fix PR10581 
llvm-svn: 137067
 2011-08-08 21:31:08 +00:00
Jim Grosbach
ffac5ceead ARM load/store label parsing. 
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064
 2011-08-08 20:59:31 +00:00
Jakob Stoklund Olesen
9451389166 Hoist hasLoadFromStackSlot and hasStoreToStackSlot. 
These the methods are target-independent since they simply scan the
memory operands.  They can live in TargetInstrInfoImpl.

llvm-svn: 137063
 2011-08-08 20:53:24 +00:00
Owen Anderson
e4638b5b2d Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0. 
llvm-svn: 137062
 2011-08-08 20:42:17 +00:00
Eli Friedman
7a34419c6f Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 
llvm-svn: 137061
 2011-08-08 19:49:37 +00:00
Benjamin Kramer
3490c59cda Pacify virtual dtor warnings and cmake buildbots. 
llvm-svn: 137060
 2011-08-08 19:09:02 +00:00
Benjamin Kramer
8c3f23ec80 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions. 
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
 2011-08-08 18:56:44 +00:00
Benjamin Kramer
d4dc8d86f4 llvm-objdump: disassembly enhancements 
- Indent simple loops
- Print unreachable blocks as .byte directives

llvm-svn: 137058
 2011-08-08 18:41:34 +00:00
Benjamin Kramer
26d5603f54 llvm-objdump: Use help of CFG to print assembly when --cfg is passed. 
This way we can avoid printing unreachable code (data).

llvm-svn: 137057
 2011-08-08 18:32:12 +00:00
Devang Patel
bc9a3e12d9 Simplify by creating parent first. 
llvm-svn: 137056
 2011-08-08 18:22:10 +00:00
Jakob Stoklund Olesen
85931574b0 Don't clobber pending ST regs when FP regs are killed. 
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

llvm-svn: 137050
 2011-08-08 17:15:43 +00:00
Bill Wendling
0f2208f619 Clean up the grammar for the landingpad instruction. 
llvm-svn: 137042
 2011-08-08 08:06:05 +00:00
Bill Wendling
ee869ce6c1 Remove unnecessary space. 
llvm-svn: 137041
 2011-08-08 08:02:48 +00:00
Bill Wendling
83c0ada603 Fix typo found by John. 
llvm-svn: 137040
 2011-08-08 07:58:58 +00:00
Chris Lattner
5099413082 strengthen up an assertion: you can't create a constant struct 
with an opaque struct type, it doesn't make sense.  This should
resolve PR10473.

llvm-svn: 137028
 2011-08-07 04:18:48 +00:00
Jakob Stoklund Olesen
32649cbc65 Fix typo. Thanks, Andy! 
llvm-svn: 137023
 2011-08-06 18:20:24 +00:00