Craig Topper
1ddf62dc2c
Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns.
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llvm-svn: 154268
2012-04-07 21:57:43 +00:00
NAKAMURA Takumi
1bfc716b7d
Target/X86/MCTargetDesc/X86MCAsmInfo.cpp: Enable DwarfCFI (aka DW2) on Cygming.
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Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.
llvm-svn: 154247
2012-04-07 02:24:20 +00:00
Benjamin Kramer
103f74e9f8
Fix narrowing conversion.
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llvm-svn: 154171
2012-04-06 13:33:52 +00:00
Craig Topper
ffae2f8986
Allow 256-bit shuffles to be split if a 128-bit lane contains elements from a single source. This is a rewrite of the 256-bit shuffle splitting code based on similar code from legalize types. Fixes PR12413.
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llvm-svn: 154166
2012-04-06 07:45:23 +00:00
Rafael Espindola
88a1aeb123
Always compute all the bits in ComputeMaskedBits.
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This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
llvm-svn: 154011
2012-04-04 12:51:34 +00:00
Craig Topper
ce6c05e0df
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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llvm-svn: 153935
2012-04-03 05:20:24 +00:00
Benjamin Kramer
2f6189e2a5
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
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All implementations used the same code.
llvm-svn: 153866
2012-04-02 08:32:38 +00:00
Craig Topper
fe02cb5e8b
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
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llvm-svn: 153863
2012-04-02 07:01:04 +00:00
Craig Topper
dbc259a436
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
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llvm-svn: 153860
2012-04-02 06:09:36 +00:00
Nadav Rotem
2729f54295
This commit contains a few changes that had to go in together.
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1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
(and also scalar_to_vector).
2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))
3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y).
4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.
Code which was previously compiled to this:
movd (%rsi), %xmm0
movdqa .LCPI0_0(%rip), %xmm2
pshufb %xmm2, %xmm0
movd (%rdi), %xmm1
pshufb %xmm2, %xmm1
pxor %xmm0, %xmm1
pshufb .LCPI0_1(%rip), %xmm1
movd %xmm1, (%rdi)
ret
Now compiles to this:
movl (%rsi), %eax
xorl %eax, (%rdi)
ret
llvm-svn: 153848
2012-04-01 19:31:22 +00:00
Benjamin Kramer
dbd6a33c45
Rip out emission of the regIsInRegClass function for the asm printer.
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It's slow, bloated and completely redundant with MCRegisterClass::contains.
llvm-svn: 153782
2012-03-30 23:13:40 +00:00
Benjamin Kramer
0365dc97a8
Add a note about a missed cmov -> sbb opportunity.
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llvm-svn: 153741
2012-03-30 13:02:58 +00:00
Lang Hames
94d892c492
Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.
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llvm-svn: 153680
2012-03-29 19:54:28 +00:00
Benjamin Kramer
e3b0c81c27
Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds.
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llvm-svn: 153643
2012-03-29 12:37:26 +00:00
Craig Topper
9a00ba461c
Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions.
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llvm-svn: 153636
2012-03-29 07:11:23 +00:00
Joel Jones
486c38b0cf
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
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This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
llvm-svn: 153635
2012-03-29 05:45:48 +00:00
Joel Jones
32f97db4b2
Reverted to revision 153616 to unblock build
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llvm-svn: 153623
2012-03-29 01:20:56 +00:00
Joel Jones
b4477ee31f
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.
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This is a code change to add support for changing instruction sequences of the form:
load
inc/dec of 8/16/32/64 bits
store
into the appropriate X86 inc/dec through memory instruction:
inc[qlwb] / dec[qlwb]
The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded.
llvm-svn: 153617
2012-03-29 00:37:47 +00:00
Craig Topper
bf6a47d0ec
Prune some includes
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llvm-svn: 153502
2012-03-27 07:54:11 +00:00
Craig Topper
6bb276ae72
Remove unnecessary llvm:: qualifications
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llvm-svn: 153500
2012-03-27 07:21:54 +00:00
Joerg Sonnenberger
4df2738e5f
Put Is64BitMemOperand into !defined(NDEBUG) for now.
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llvm-svn: 153185
2012-03-21 14:09:26 +00:00
Benjamin Kramer
ad9527ea4c
Use a signed value for this enum to avoid spuriuos warnings from gcc.
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llvm-svn: 153184
2012-03-21 13:48:11 +00:00
Joerg Sonnenberger
82af1c8704
Fix generation of the address size override prefix. Add assertions for
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the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
llvm-svn: 153166
2012-03-21 05:48:07 +00:00
Craig Topper
32b2c8fecc
Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
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llvm-svn: 153154
2012-03-21 02:14:01 +00:00
Chad Rosier
17f25ea47b
[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to
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vextractf128 with 128-bit mem dest.
Combines
vextractf128 $0, %ymm0, %xmm0
vmovaps %xmm0, (%rdi)
to
vextractf128 $0, %ymm0, (%rdi)
rdar://11082570
llvm-svn: 153139
2012-03-20 21:43:40 +00:00
Chad Rosier
f6d522341c
[avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give
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precedence over the VINSERTF128 avx1 patterns.
llvm-svn: 153114
2012-03-20 19:45:07 +00:00
Chad Rosier
73d8191b27
Whitespace.
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llvm-svn: 153105
2012-03-20 18:38:33 +00:00
Chad Rosier
ffd2dbd676
[avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove
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whitespace from test case. No functional change intended.
llvm-svn: 153103
2012-03-20 18:24:55 +00:00
Chad Rosier
143f33dc92
[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
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This results in things such as
vmovups 16(%rdi), %xmm0
vinsertf128 $1, %xmm0, %ymm0, %ymm0
to be combined to
vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
rdar://11076953
llvm-svn: 153092
2012-03-20 17:08:51 +00:00
Craig Topper
61aa773498
Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
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llvm-svn: 153080
2012-03-20 07:17:59 +00:00
Craig Topper
de938c64eb
Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
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llvm-svn: 153079
2012-03-20 06:42:26 +00:00
Preston Gurd
d1ae391210
This patch adds X86 instruction itineraries for non-pseudo opcodes in
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X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
llvm-svn: 153033
2012-03-19 14:10:12 +00:00
Benjamin Kramer
080ccc13a6
Add a note for -ffast-math optimization of vector norm.
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llvm-svn: 153031
2012-03-19 00:43:34 +00:00
Craig Topper
34891f519c
isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.
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llvm-svn: 153027
2012-03-18 22:50:10 +00:00
Craig Topper
b1f171a213
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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llvm-svn: 152997
2012-03-17 18:46:09 +00:00
Chad Rosier
bd3e55d39c
[avx] Add patterns for VINSERTF128rm.
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This results in things such as
vmovaps -96(%rbx), %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
to be combined to
vinsertf128 $1, -96(%rbx), %ymm0, %ymm0
rdar://10643481
llvm-svn: 152762
2012-03-15 00:45:30 +00:00
Kevin Enderby
b5413ed6cc
Change the X86 assembler to not require a segment register on string
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instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
llvm-svn: 152654
2012-03-13 19:47:55 +00:00
Kevin Enderby
9f26c75ab5
Added a missing error check for X86 assembly with mismatched base and index
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registers not both being 64-bit or both being 32-bit registers.
llvm-svn: 152580
2012-03-12 21:32:09 +00:00
Craig Topper
df2bf795d6
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
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llvm-svn: 152538
2012-03-11 07:57:25 +00:00
Kay Tiong Khoo
aaa4140718
*fix typo in comment; test of commit access
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llvm-svn: 152507
2012-03-10 21:29:49 +00:00
Benjamin Kramer
ae4fd1b853
C files in llvm still have to be C89 compliant, remove C++-style comments.
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llvm-svn: 152495
2012-03-10 15:10:06 +00:00
Bill Wendling
1a3f2619a7
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
llvm-svn: 152487
2012-03-10 07:37:27 +00:00
Kevin Enderby
15f974a5a4
Add the missing call to Error when a bad X86 scale expression is parsed.
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llvm-svn: 152443
2012-03-09 22:24:10 +00:00
Kevin Enderby
1a3b6570f8
Fix the x86 disassembler to at least print the lock prefix if it is the first
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
2012-03-09 17:52:49 +00:00
Craig Topper
3dee24b8c3
Use uint16_t to store opcodes in static tables in X86 backend.
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llvm-svn: 152391
2012-03-09 07:45:21 +00:00
Chad Rosier
a10cf5e1b9
Fix a regression from r147481.
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Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078
llvm-svn: 152366
2012-03-09 02:00:48 +00:00
Eli Friedman
c397259ea6
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
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llvm-svn: 152136
2012-03-06 19:58:46 +00:00
Jim Grosbach
2eea383b12
Make MCRegisterInfo available to the the MCInstPrinter.
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Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
2012-03-05 19:33:20 +00:00
Chad Rosier
f2e436b74f
Address Evan's comments for r151877.
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Specifically, remove the magic number when checking to see if the copy has a
glue operand and simplify the checking logic.
rdar://10930395
llvm-svn: 152041
2012-03-05 19:27:12 +00:00
Eli Friedman
4a049305a9
Make aliases for shld and shrd match gas. PR12173.
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llvm-svn: 152014
2012-03-05 04:31:54 +00:00