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8143 Commits

Author SHA1 Message Date
Benjamin Kramer
9a10a94e1a Don't mix declarations and code. 
llvm-svn: 150305
 2012-02-11 16:01:02 +00:00
Benjamin Kramer
44e872829d Make the EDis tables const. 
llvm-svn: 150304
 2012-02-11 14:51:07 +00:00
Benjamin Kramer
675a84a6ea Reuse the enum names from X86Desc in the X86Disassembler. 
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303
 2012-02-11 14:50:54 +00:00
Craig Topper
59398d7eb3 Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel. 
llvm-svn: 150299
 2012-02-11 07:43:35 +00:00
Craig Topper
64d1a36ad0 Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. 
llvm-svn: 150296
 2012-02-11 06:24:48 +00:00
Craig Topper
c20605c287 More tweaks to get the size of the X86 disassembler tables down. 
llvm-svn: 150167
 2012-02-09 08:58:07 +00:00
Craig Topper
82b0ee4558 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
llvm-svn: 150161
 2012-02-09 07:45:30 +00:00
Jakob Stoklund Olesen
27f005d12d Handle register masks when searching for EFLAGS clobbers. 
Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

llvm-svn: 150117
 2012-02-09 00:17:22 +00:00
Elena Demikhovsky
87a6e08d3a Fixed a bug in printing "cmp" pseudo ops. 
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.

llvm-svn: 150068
 2012-02-08 08:37:26 +00:00
Craig Topper
f19c739d2d Remove a couple unneeded intrinsic patterns 
llvm-svn: 150067
 2012-02-08 08:29:30 +00:00
Craig Topper
6dbd5e534c Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
llvm-svn: 150060
 2012-02-08 06:36:57 +00:00
Evan Cheng
ab4ad855cc Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang. 
llvm-svn: 150008
 2012-02-07 22:50:41 +00:00
Craig Topper
a8a69356e1 Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
llvm-svn: 149968
 2012-02-07 06:28:42 +00:00
Derek Schuff
f522835510 Enable streaming of bitcode 
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.

llvm-svn: 149918
 2012-02-06 22:30:29 +00:00
Chris Lattner
7a6bd0185e Remove some dead code and tidy things up now that vectors use ConstantDataVector 
instead of always using ConstantVector.

llvm-svn: 149912
 2012-02-06 21:56:39 +00:00
Benjamin Kramer
3443a8294a X86: Don't call malloc for 4 bits. No functionality change. 
llvm-svn: 149866
 2012-02-06 12:06:18 +00:00
Craig Topper
74416bcd0e Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding. 
llvm-svn: 149859
 2012-02-06 07:17:51 +00:00
Duncan Sands
cc472eec96 Persuade GCC that there is nothing worth warning about here (there isn't). 
llvm-svn: 149834
 2012-02-05 14:20:11 +00:00
Chandler Carruth
9db1b1bb0a Begin fleshing out more convenience predicates in llvm::Triple and 
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.

This round of predicates is focused on OS-categorization predicates.

llvm-svn: 149815
 2012-02-05 08:26:40 +00:00
Craig Topper
dfa8617ab9 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Craig Topper
fe4a950689 Convert assert(0) to llvm_unreachable in X86 Target directory. 
llvm-svn: 149809
 2012-02-05 05:38:58 +00:00
Craig Topper
7b7867bbaa Convert some assert(0) in default of switch statements to llvm_unreachable. 
llvm-svn: 149808
 2012-02-05 03:43:23 +00:00
Craig Topper
07b9d056fa Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
llvm-svn: 149807
 2012-02-05 03:14:49 +00:00
Craig Topper
c289726019 Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. 
llvm-svn: 149795
 2012-02-05 00:55:56 +00:00
Andrew Trick
fb574d1c19 TargetPassConfig: confine the MC configuration to TargetMachine. 
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

llvm-svn: 149754
 2012-02-04 02:56:59 +00:00
Craig Topper
dee5f41723 Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation. 
llvm-svn: 149683
 2012-02-03 06:52:33 +00:00
Craig Topper
afb89fb5f9 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. 
llvm-svn: 149680
 2012-02-03 06:32:21 +00:00
Andrew Trick
da0c52e742 Added TargetPassConfig. The first little step toward configuring codegen passes. 
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

llvm-svn: 149672
 2012-02-03 05:12:41 +00:00
Andrew Trick
0838f6788a whitespace 
llvm-svn: 149671
 2012-02-03 05:12:30 +00:00
Lang Hames
311e44bd42 Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957. 
llvm-svn: 149655
 2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
b84880cf78 Require non-NULL register masks. 
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646
 2012-02-02 23:52:57 +00:00
Elena Demikhovsky
00f62e0e9f Minor change in signature of the getZeroVector() 
llvm-svn: 149601
 2012-02-02 09:20:18 +00:00
Elena Demikhovsky
7ca11b6e3f Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.

llvm-svn: 149600
 2012-02-02 09:10:43 +00:00
Francois Pichet
0f41b565e8 Unbreak the MSVC build. 
llvm-svn: 149599
 2012-02-02 08:36:09 +00:00
Lang Hames
004f627ed6 Set EFLAGS correctly in EmitLoweredSelect on X86. 
llvm-svn: 149597
 2012-02-02 07:48:37 +00:00
Andrew Trick
d09b64fc25 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Mon P Wang
7313ffe333 Avoid creating an extract element to an illegal type after LegalizeTypes has run. 
llvm-svn: 149548
 2012-02-01 22:15:20 +00:00
Chad Rosier
9c3c30332f Tidy up. 
llvm-svn: 149521
 2012-02-01 18:45:51 +00:00
Elena Demikhovsky
455db87d41 Passing AVX 256-bit structures in Win64 was wrong. 
Fixed Win64 calling conventions.

llvm-svn: 149494
 2012-02-01 10:46:14 +00:00
Elena Demikhovsky
f63bfb1b5d Shortened code in shuffle masks 
llvm-svn: 149493
 2012-02-01 10:33:05 +00:00
Elena Demikhovsky
da37eb48d8 Optimization for "truncate" operation on AVX. 
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.

llvm-svn: 149485
 2012-02-01 07:56:44 +00:00
Craig Topper
79859da905 Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900. 
llvm-svn: 149478
 2012-02-01 06:51:58 +00:00
Devang Patel
b8688eac99 Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly. 
llvm-svn: 149396
 2012-01-31 18:14:05 +00:00
Craig Topper
2b764de6ab Remove pcmpgt/pcmpeq intrinsics as clang is not using them. 
llvm-svn: 149367
 2012-01-31 06:52:44 +00:00
Evan Cheng
111c0844d5 PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina. 
llvm-svn: 149294
 2012-01-30 23:10:32 +00:00
Devang Patel
be1817e3e0 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
llvm-svn: 149291
 2012-01-30 22:47:12 +00:00
Devang Patel
a5bfdedb9f Intel syntax. Support .intel_syntax directive. 
llvm-svn: 149270
 2012-01-30 20:02:42 +00:00
Benjamin Kramer
0a88f2966a Fix refacto. 
llvm-svn: 149269
 2012-01-30 20:01:35 +00:00
Douglas Gregor
9deae777e2 Eliminate narrowing conversion in initializer list, to make C++11 happy 
llvm-svn: 149254
 2012-01-30 16:57:18 +00:00
Benjamin Kramer
af9ce50196 X86: Simplify shuffle mask generation code. 
llvm-svn: 149248
 2012-01-30 15:16:21 +00:00
Craig Topper
9a8c6c1633 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
llvm-svn: 149232
 2012-01-30 07:50:31 +00:00
Craig Topper
9aabdda961 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes. 
llvm-svn: 149216
 2012-01-30 01:10:15 +00:00
Devang Patel
e4725ba181 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Craig Topper
9259da4826 Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
llvm-svn: 149122
 2012-01-27 07:09:40 +00:00
Jim Grosbach
e6ac20aadf Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
Jakob Stoklund Olesen
c63a45ebe6 Handle call-clobbered ymm registers on Win64. 
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.

Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered.  This allows live xmm
registers across calls.

This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.

llvm-svn: 149088
 2012-01-26 22:59:28 +00:00
Victor Umansky
bf35274368 Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
 2012-01-26 08:51:39 +00:00
Craig Topper
8f8e428400 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns. 
llvm-svn: 149054
 2012-01-26 07:51:55 +00:00
Craig Topper
814a037ac6 Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
llvm-svn: 149053
 2012-01-26 07:31:30 +00:00
Craig Topper
7ed643d290 Remove some more patterns by custom lowering intrinsics to target specific nodes. 
llvm-svn: 149052
 2012-01-26 07:18:03 +00:00
Chris Lattner
a6642a918d fix a bug I introduced in r148929, this is not a splat! 
Thanks to Eli for noticing.

llvm-svn: 148947
 2012-01-25 09:56:22 +00:00
Craig Topper
c2b030401c Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
llvm-svn: 148933
 2012-01-25 06:43:11 +00:00
Chris Lattner
473bdbaabc use ConstantVector::getSplat in a few places. 
llvm-svn: 148929
 2012-01-25 06:02:56 +00:00
Craig Topper
9edaa5c15a Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
llvm-svn: 148927
 2012-01-25 05:37:32 +00:00
Craig Topper
c968a4ccc9 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
llvm-svn: 148922
 2012-01-25 04:42:03 +00:00
Craig Topper
f4166abe42 Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
llvm-svn: 148914
 2012-01-25 03:52:09 +00:00
Devang Patel
0da753c9e6 Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Elena Demikhovsky
ee8c87b433 ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803
 2012-01-24 13:54:13 +00:00
Craig Topper
7311a89449 Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types. 
llvm-svn: 148771
 2012-01-24 03:03:17 +00:00
Devang Patel
48ee4a8277 Fix typo. 
llvm-svn: 148751
 2012-01-23 23:56:33 +00:00
Devang Patel
327773a25b Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Devang Patel
3c6289f43a Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Devang Patel
9698de5bf3 Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
Craig Topper
606872615f Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
llvm-svn: 148687
 2012-01-23 08:18:28 +00:00
Craig Topper
9a78ce373d Update more places to use target specific nodes for vector shifts instead of intrinsics. 
llvm-svn: 148685
 2012-01-23 06:46:22 +00:00
Craig Topper
360c9f28cf Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
llvm-svn: 148684
 2012-01-23 06:16:53 +00:00
Craig Topper
03b49e88a2 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
llvm-svn: 148672
 2012-01-23 00:06:44 +00:00
Craig Topper
b80bb890b6 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
llvm-svn: 148670
 2012-01-22 23:36:02 +00:00
Craig Topper
558395cb4e Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
llvm-svn: 148667
 2012-01-22 22:42:16 +00:00
Craig Topper
2b6951f7c4 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
llvm-svn: 148664
 2012-01-22 19:15:14 +00:00
Craig Topper
5e9b6de71f Make code a little less verbose. 
llvm-svn: 148651
 2012-01-22 03:07:48 +00:00
Craig Topper
eaca0c20ea Remove unused X86 ISD node type defines. 
llvm-svn: 148644
 2012-01-22 01:15:56 +00:00
Craig Topper
bb07c0da2d Move some vector shift patterns into their instruction definitions. 
llvm-svn: 148643
 2012-01-22 00:41:20 +00:00
Craig Topper
63c59673a3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions. 
llvm-svn: 148641
 2012-01-21 18:37:15 +00:00
Benjamin Kramer
bdd152e9cf Remove unused variables. 
llvm-svn: 148635
 2012-01-21 10:42:44 +00:00
Craig Topper
d493ca92c4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. 
llvm-svn: 148632
 2012-01-21 08:49:33 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
llvm-svn: 148569
 2012-01-20 21:14:06 +00:00
Craig Topper
7b50829b7f Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. 
llvm-svn: 148537
 2012-01-20 09:29:03 +00:00
Craig Topper
e2d3f3060d Add support for selecting 256-bit PALIGNR. 
llvm-svn: 148532
 2012-01-20 05:53:00 +00:00
Eli Friedman
ffa3b8b5f1 Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. 
llvm-svn: 148513
 2012-01-20 00:05:46 +00:00
Devang Patel
b42cea31aa Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Craig Topper
cee7bd6b73 Folding table additions and fixes for AVX. 
llvm-svn: 148467
 2012-01-19 08:50:38 +00:00
Craig Topper
3d928aa51b Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. 
llvm-svn: 148466
 2012-01-19 08:19:12 +00:00
Nick Lewycky
c1e7e2eaf6 Add a TargetOption for disabling tail calls. 
llvm-svn: 148442
 2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
498e016c87 Add experimental -x86-use-regmask command line option. 
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438
 2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
85ef53eb8d Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
 2012-01-18 23:52:19 +00:00
Devang Patel
ee49d825b1 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Jim Grosbach
f88f0b08c4 Tidy up. MCAsmBackend naming conventions. 
llvm-svn: 148400
 2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
e9c53bc69b Add a CoveredBySubRegs property to Register descriptions. 
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
 2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
fbb3f38a1a Move X86 callee saved register lists to the X86CallConv .td file. 
Add a trivial implementation of the getCallPreservedMask() hook.

llvm-svn: 148347
 2012-01-17 22:47:01 +00:00
Devang Patel
e03a4f051f Intel syntax: Fix parser match class to check memory operand size. 
llvm-svn: 148338
 2012-01-17 21:48:03 +00:00
Devang Patel
4585b536ee Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
llvm-svn: 148334
 2012-01-17 21:25:10 +00:00
Devang Patel
91c178c1f7 Untabify. 
llvm-svn: 148322
 2012-01-17 19:09:22 +00:00
Devang Patel
388aa8feb0 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
llvm-svn: 148321
 2012-01-17 19:08:07 +00:00
Devang Patel
b1e07175c4 Intel syntax: Robustify memory operand parsing. 
llvm-svn: 148312
 2012-01-17 18:00:18 +00:00
Nadav Rotem
ab6d6e6d56 Fix warning. 
llvm-svn: 148301
 2012-01-17 09:31:09 +00:00
Nadav Rotem
c460c870b2 Fix 11769. 
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.

llvm-svn: 148298
 2012-01-17 09:13:19 +00:00
Craig Topper
c1c438b32f Remove unnecessary AVX check from an assert. hasSSE2 is enough. 
llvm-svn: 148295
 2012-01-17 08:23:44 +00:00
Craig Topper
e230e9df7d Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772. 
llvm-svn: 148285
 2012-01-17 04:44:50 +00:00
Eli Friedman
a343d87eac Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768. 
llvm-svn: 148240
 2012-01-16 16:42:21 +00:00
Eli Friedman
a2b480b010 Get rid of unused codegen-only instruction. 
llvm-svn: 148239
 2012-01-16 16:29:35 +00:00
Craig Topper
d1f51dc860 Give priority to AVX over SSE for 128-bit floating point unpck instructions. 
llvm-svn: 148233
 2012-01-16 09:56:42 +00:00
Nadav Rotem
b36c029e3b [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. 
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.

llvm-svn: 148225
 2012-01-15 19:27:55 +00:00
Benjamin Kramer
14443a8cf6 Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen. 
llvm-svn: 148218
 2012-01-15 13:16:05 +00:00
Craig Topper
0c4ab86d2c Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. 
llvm-svn: 148196
 2012-01-14 18:29:57 +00:00
Craig Topper
ddc2e1091e Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions. 
llvm-svn: 148194
 2012-01-14 18:14:53 +00:00
Chad Rosier
4a705ae81a Fix pasto from r146196. 
llvm-svn: 148167
 2012-01-14 01:50:21 +00:00
Devang Patel
410d6214f9 Revert r148131, it was committed before it was ready. 
llvm-svn: 148134
 2012-01-13 19:28:58 +00:00
Devang Patel
194ad5ead8 Refactor. 
llvm-svn: 148131
 2012-01-13 19:12:18 +00:00
Craig Topper
c1e3d46e07 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. 
llvm-svn: 148112
 2012-01-13 09:21:41 +00:00
Craig Topper
e75115a861 use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. 
llvm-svn: 148109
 2012-01-13 08:32:21 +00:00
Craig Topper
e52c0484de Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. 
llvm-svn: 148108
 2012-01-13 08:12:35 +00:00
Craig Topper
71ea42cc29 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. 
llvm-svn: 148106
 2012-01-13 06:59:47 +00:00
Craig Topper
0e34a8e58c Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750. 
llvm-svn: 148101
 2012-01-13 06:12:41 +00:00
Craig Topper
32812741b7 Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. 
llvm-svn: 148096
 2012-01-13 05:04:25 +00:00
Bill Wendling
c8f27fdf02 Fix off-by-one error. 
llvm-svn: 148077
 2012-01-13 00:41:53 +00:00
Bill Wendling
ce528914e7 Fix the code that was WRONG. 
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.

llvm-svn: 148064
 2012-01-12 23:05:03 +00:00
Elena Demikhovsky
beb66de0f9 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.

llvm-svn: 148044
 2012-01-12 20:33:10 +00:00
Rafael Espindola
959adf57db Support segmented stacks on 64-bit FreeBSD. 
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

llvm-svn: 148041
 2012-01-12 20:24:30 +00:00
Rafael Espindola
dda46f4081 Support segmented stacks on win32. 
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

llvm-svn: 148040
 2012-01-12 20:22:08 +00:00
Devang Patel
d568674834 Rename X86ATTAsmParser -> X86AsmParser 
We are using one parser to parse att as well as intel style syntax.

llvm-svn: 148032
 2012-01-12 18:03:40 +00:00
Benjamin Kramer
7678692172 After Jakob's r147938 exception handling on i386 was completely broken. 
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

llvm-svn: 148030
 2012-01-12 17:37:18 +00:00
Nadav Rotem
618722de09 Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors. 
The attached testcase was stuck in an endless loop.

llvm-svn: 148027
 2012-01-12 15:31:55 +00:00
Benjamin Kramer
ae4ad5f924 X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. 
llvm-svn: 148024
 2012-01-12 12:41:34 +00:00
Devang Patel
2096c1a697 Add predicate method check match memory operand size, if available. 
In att style asm syntax memory operand size is derived from suffix attached with mnemonic.  In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.

llvm-svn: 148006
 2012-01-12 01:51:42 +00:00
Devang Patel
ed9a353b59 Add intel style operand parser skeleton. 
This is a work in progress.

llvm-svn: 148002
 2012-01-12 01:36:43 +00:00
Chandler Carruth
751438a272 Switch all of the uses of my InsertDAGNode helper to follow the exact 
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.

I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.

I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.

llvm-svn: 148001
 2012-01-12 01:34:44 +00:00
Rafael Espindola
cd3a456eef Support segmented stacks on mac. 
This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support
frames with static size
Patch by Brian Anderson.

llvm-svn: 147960
 2012-01-11 19:00:37 +00:00
Rafael Espindola
f7e3528d92 Generate the segmented stack prologue for fastcc too. 
Patch by Brian Anderson.

llvm-svn: 147958
 2012-01-11 18:41:19 +00:00
Chandler Carruth
e3facd7860 Revert r147945 which disabled an addressing mode transformation. I had 
hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.

If anyone else is seeing failures, please let me know!

llvm-svn: 147957
 2012-01-11 18:36:12 +00:00
Rafael Espindola
12313ca273 Use unsigned comparison in segmented stack prologue. 
This is a comparison of two addresses, and GCC does the comparison unsigned.

Patch by Brian Anderson.

llvm-svn: 147954
 2012-01-11 18:23:35 +00:00
Rafael Espindola
dd2f5fe210 Explicitly set the scale to 1 on some segstack prologue instrs. 
Patch by Brian Anderson.

llvm-svn: 147952
 2012-01-11 18:14:03 +00:00
Jan Sjödin
cb98434ebe Add XOP Intrinsics and tests 
llvm-svn: 147949
 2012-01-11 15:20:20 +00:00
Nadav Rotem
01bf090299 Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead. 
llvm-svn: 147948
 2012-01-11 14:07:51 +00:00
Chandler Carruth
e443e5e55d Disable the transformation I added in r147936 to see if it fixes some 
strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.

llvm-svn: 147945
 2012-01-11 12:17:47 +00:00