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192 Commits

Author SHA1 Message Date
Evan Cheng
bdb85b387f Support for scalar to vector with zero extension. 
llvm-svn: 27091
 2006-03-24 23:15:12 +00:00
Evan Cheng
d58d54cf3e Handle BUILD_VECTOR with all zero elements. 
llvm-svn: 27056
 2006-03-24 07:29:27 +00:00
Evan Cheng
3028b04057 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
llvm-svn: 27040
 2006-03-24 02:58:06 +00:00
Evan Cheng
68410804f0 Handle more shuffle cases with SHUFP* instructions. 
llvm-svn: 27024
 2006-03-24 01:18:28 +00:00
Evan Cheng
54215cd1ea Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.

llvm-svn: 26964
 2006-03-22 22:07:06 +00:00
Evan Cheng
cff38e19c3 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
 2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00
Evan Cheng
cb9fb051a5 - Clean up the lowering and selection code of ConstantPool, GlobalAddress, 
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335
 2006-02-23 20:41:18 +00:00
Evan Cheng
2977507828 PIC related bug fixes. 
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324
 2006-02-23 02:43:52 +00:00
Chris Lattner
6bb2c3e9cd split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner
a124432746 Updates to match change of getRegForInlineAsmConstraint prototype 
llvm-svn: 26305
 2006-02-21 23:11:00 +00:00
Evan Cheng
bf3558a375 x86 / Darwin PIC support. 
llvm-svn: 26273
 2006-02-18 00:15:05 +00:00
Nate Begeman
9c0ab71f4a kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Nate Begeman
0bc71999b9 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Evan Cheng
078962656b Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a 
flag so it can be flagged to a FST.

llvm-svn: 25953
 2006-02-04 02:20:30 +00:00
Evan Cheng
45ebd632f2 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.

llvm-svn: 25857
 2006-01-31 22:28:30 +00:00
Chris Lattner
5587b270e4 * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
 2006-01-31 19:43:35 +00:00
Evan Cheng
49467b6b5b Added custom lowering of fabs 
llvm-svn: 25831
 2006-01-31 03:14:29 +00:00
Evan Cheng
d2d96373dc Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
 2006-01-30 08:02:57 +00:00
Chris Lattner
a44182300b Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner
754bc1f46c adjust prototype 
llvm-svn: 25798
 2006-01-30 03:49:07 +00:00
Nate Begeman
d2c6fbef4a Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
 2006-01-27 21:09:22 +00:00
Evan Cheng
5891f49c47 x86 CPU detection and proper subtarget support 
llvm-svn: 25679
 2006-01-27 08:10:46 +00:00
Nate Begeman
c29fac7fce First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
 2006-01-25 18:21:52 +00:00
Evan Cheng
794a7cf6fe Fix sint_to_fp (fild*) support. 
llvm-svn: 25257
 2006-01-12 22:54:21 +00:00
Evan Cheng
66540aa32c Support for MEMCPY and MEMSET. 
llvm-svn: 25226
 2006-01-11 22:15:48 +00:00
Evan Cheng
9adc8e5a3d SSE cmov support. 
llvm-svn: 25190
 2006-01-11 00:33:36 +00:00
Evan Cheng
d3babfe458 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. 
llvm-svn: 25158
 2006-01-09 18:33:28 +00:00
Evan Cheng
1e0d7b98f3 * Fast call support. 
* FP cmp, setcc, etc.

llvm-svn: 25117
 2006-01-06 00:43:03 +00:00
Evan Cheng
2329411038 DAG based isel call support. 
llvm-svn: 25103
 2006-01-05 00:27:02 +00:00
Evan Cheng
995503fc91 More X86 floating point patterns. 
llvm-svn: 24990
 2005-12-23 07:31:11 +00:00
Evan Cheng
fb6413e05a * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Evan Cheng
6f15189a77 * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
 2005-12-21 20:21:51 +00:00
Evan Cheng
0226113ed5 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng
44e4e6a57f Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Evan Cheng
bb34a50cb0 X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Evan Cheng
d51da93a03 X86 lowers SELECT to a cmp / test followed by a conditional move. 
llvm-svn: 24754
 2005-12-17 01:21:05 +00:00
Andrew Lenharth
a369904fc5 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner
792ac11aee Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch 
contributed by Evan Cheng.

llvm-svn: 24358
 2005-11-15 00:40:23 +00:00