Jakob Stoklund Olesen
024a1de4ae
Use basic block numbers as indexes when mapping slot index ranges.
...
This is more compact and faster than using DenseMap.
llvm-svn: 128763
2011-04-02 06:03:31 +00:00
Cameron Zwarich
9573b6277e
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
...
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
llvm-svn: 128759
2011-04-02 02:40:43 +00:00
Cameron Zwarich
2748634089
Add a RemoveFromWorklist method to DCI. This is needed to do some complicated
...
transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.
llvm-svn: 128758
2011-04-02 02:40:26 +00:00
Johnny Chen
dcd29e054c
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
Akira Hatanaka
9a001f303e
Undo changes mistakenly made in revision 128750.
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llvm-svn: 128751
2011-04-02 00:26:12 +00:00
Akira Hatanaka
6b700f35aa
Insert space before ';' to prevent warnings.
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llvm-svn: 128750
2011-04-02 00:15:58 +00:00
Johnny Chen
6f10cfdf01
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
Johnny Chen
b308662930
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
Johnny Chen
845caa871c
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
Benjamin Kramer
d91d0d877e
Fix comment.
...
llvm-svn: 128745
2011-04-01 22:29:18 +00:00
Benjamin Kramer
eb9bd6ed23
Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:
...
- Localize the check if an icmp has one use to a place where we know we're
introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
folded away earlier.
- Fix a typo.
llvm-svn: 128744
2011-04-01 22:22:11 +00:00
Evan Cheng
4531994839
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
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llvm-svn: 128743
2011-04-01 22:09:28 +00:00
Akira Hatanaka
9f4b4d2dc1
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
Akira Hatanaka
9257b524eb
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
Oscar Fuentes
95454be82a
CMake: remove debug code from previous commit.
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llvm-svn: 128740
2011-04-01 21:39:38 +00:00
Owen Anderson
48048d179c
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
...
llvm-svn: 128739
2011-04-01 21:07:39 +00:00
Jim Grosbach
039844acc5
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
...
llvm-svn: 128736
2011-04-01 20:26:57 +00:00
Daniel Dunbar
7e8cb9fc5e
tlbgen/MC: StringRef's to temporary objects considered harmful.
...
llvm-svn: 128735
2011-04-01 20:23:52 +00:00
Johnny Chen
65fe34ae00
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
Benjamin Kramer
09e0a56ebc
Fix build.
...
llvm-svn: 128733
2011-04-01 20:15:16 +00:00
Benjamin Kramer
7c0178b9ec
InstCombine: Turn icmp + sext into bitwise/integer ops when the input has only one unknown bit.
...
int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }
before (x86_64):
_test1:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
ret
_test3:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
notl %eax
ret
after:
_test1:
shrl $3, %edi
andl $1, %edi
leal -1(%rdi), %eax
ret
_test3:
shll $28, %edi
movl %edi, %eax
sarl $31, %eax
ret
llvm-svn: 128732
2011-04-01 20:09:10 +00:00
Benjamin Kramer
d74739be04
InstCombine: Move (sext icmp) transforms into their own method. No intended functionality change.
...
llvm-svn: 128731
2011-04-01 20:09:03 +00:00
Evan Cheng
28382f9178
Add comments.
...
llvm-svn: 128730
2011-04-01 19:57:01 +00:00
Evan Cheng
13c73e4836
Assign node order numbers to results of call instruction lowering. This should improve src line debug info when sdisel is used. rdar://9199118
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llvm-svn: 128728
2011-04-01 19:42:22 +00:00
Oscar Fuentes
b5bbbd9889
Fix assignment of -fPIC to CMAKE_C_FLAGS. Configure llvm-config.in.in
...
with the contents of CMAKE_C(XX)_FLAGS too, else `llvm-config
--c(xx)flags' doesn't tell the absolute truth.
This comes from PR9603 and is based on a patch by Ryuta Suzuki!
llvm-svn: 128727
2011-04-01 19:36:06 +00:00
Akira Hatanaka
0b476a8e81
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
...
llvm-svn: 128724
2011-04-01 18:57:38 +00:00
Johnny Chen
17f1f7c322
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
...
rdar://problem/9219356
llvm-svn: 128722
2011-04-01 18:26:38 +00:00
Devang Patel
0fda72d125
Update CMakeLists.txt
...
Patch by arrowdoger.
llvm-svn: 128719
2011-04-01 18:03:58 +00:00
Akira Hatanaka
c2d74b05ca
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
Benjamin Kramer
aff6a9e50a
Initialize HasVMLxForwarding.
...
llvm-svn: 128709
2011-04-01 09:20:31 +00:00
Jay Foad
279116b009
Various Instructions' resizeOperands() methods are only used to grow the
...
list of operands. Simplify and rename them accordingly.
llvm-svn: 128708
2011-04-01 08:00:58 +00:00
Evan Cheng
830f695385
Add test case.
...
llvm-svn: 128707
2011-04-01 06:27:25 +00:00
Evan Cheng
985215c699
FileCheck'ify test.
...
llvm-svn: 128706
2011-04-01 03:36:33 +00:00
Duncan Sands
e2ed6e1116
While testing dragonegg I noticed that isCastable and getCastOpcode
...
had gotten out of sync: isCastable didn't think it was possible to
cast the x86_mmx type to anything, while it did think it possible
to cast an i64 to x86_mmx.
llvm-svn: 128705
2011-04-01 03:34:54 +00:00
Andrew Trick
5d212b6374
Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
...
llvm-svn: 128703
2011-04-01 02:22:47 +00:00
Andrew Trick
ee4b7e695a
whitespace
...
llvm-svn: 128701
2011-04-01 01:56:55 +00:00
Evan Cheng
39574b2766
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
...
rdar://8911343
llvm-svn: 128696
2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
2520bb8022
Remove unused variables
...
llvm-svn: 128692
2011-04-01 00:06:01 +00:00
Jakob Stoklund Olesen
369e673289
Fix Thumb and Thumb2 tests to be register allocator independent.
...
llvm-svn: 128690
2011-03-31 23:31:50 +00:00
Bruno Cardoso Lopes
d285a7f27e
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
203727c92e
The basic register allocator must also use the inline spiller.
...
It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.
llvm-svn: 128688
2011-03-31 23:02:17 +00:00
Jakob Stoklund Olesen
5421130bfc
Provide a legal pointer register class when targeting thumb1.
...
The LocalStackSlotAllocation pass was creating illegal registers.
llvm-svn: 128687
2011-03-31 23:02:15 +00:00
Jakob Stoklund Olesen
26236c8554
Fix SystemZ tests
...
llvm-svn: 128686
2011-03-31 23:02:12 +00:00
Nadav Rotem
897b838d5f
Instcombile optimization: extractelement(cast) -> cast(extractelement)
...
llvm-svn: 128683
2011-03-31 22:57:29 +00:00
Jakob Stoklund Olesen
33f01d005c
Fix ARM tests to be register allocator independent.
...
llvm-svn: 128680
2011-03-31 22:14:03 +00:00
Benjamin Kramer
22bdd799ee
InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't even try.
...
Thanks Eli!
llvm-svn: 128676
2011-03-31 21:35:49 +00:00
Johnny Chen
a7312b9622
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
...
amounts to an UNDEFINED instruction.
llvm-svn: 128668
2011-03-31 20:54:30 +00:00
Evan Cheng
64850406cf
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
...
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
llvm-svn: 128665
2011-03-31 19:38:48 +00:00
Johnny Chen
2c5149791a
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
llvm-svn: 128662
2011-03-31 19:28:35 +00:00
Jakob Stoklund Olesen
36c7c9d42d
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
...
Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
2011-03-31 18:42:43 +00:00