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Commit Graph

162822 Commits

Author SHA1 Message Date
Roman Lebedev
1f5fecf693 [InstCombine][NFC] Regenerate logical-select.ll test
llvm-svn: 330017
2018-04-13 14:07:29 +00:00
Clement Courbet
1a9d61356a [llvm-exegesis] Create test files in temporary directory.
Currently the test fails in sandboxed environnements.

llvm-svn: 330015
2018-04-13 13:37:07 +00:00
Sander de Smalen
9f0017c23c [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45432

llvm-svn: 330014
2018-04-13 12:56:14 +00:00
Simon Pilgrim
f11bee0ad9 [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)
llvm-svn: 330013
2018-04-13 12:50:31 +00:00
Ivan A. Kosarev
94f22e4959 [NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction
Differential Revision: https://reviews.llvm.org/D45514

llvm-svn: 330011
2018-04-13 12:45:12 +00:00
Clement Courbet
7bc87a6a65 Partially revert r330008.
llvm-svn: 330010
2018-04-13 12:43:55 +00:00
Clement Courbet
e9da1f048c [llvm-exegesis] Run unit tests on more platforms.
Summary:
 - Target-independent tests are run all the time.
 - Tests that codegen X86 code are run when X86 is in build targets.
 - Tests that run X86 jitted code are run only on X86 hosts.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D45614

llvm-svn: 330008
2018-04-13 12:20:30 +00:00
Roman Lebedev
eb86c3d76f [InstCombine][NFC] Add last few tests with constant mask for masked merge folding.
A followup for rL330003
https://bugs.llvm.org/show_bug.cgi?id=6773

llvm-svn: 330007
2018-04-13 12:00:00 +00:00
Hiroshi Inoue
1306e55fc7 [NFC] fix trivial typos in comments
"the the" -> "the", "we we" -> "we", etc

llvm-svn: 330006
2018-04-13 11:37:06 +00:00
Roman Lebedev
96630a884d [InstCombine][NFC] Add tests for masked merge folding.
https://bugs.llvm.org/show_bug.cgi?id=6773

As discussed there, some backends may want to undo this fold
(x86+bmi for scalars, x86+sse for vectors, ...)
https://bugs.llvm.org/show_bug.cgi?id=37104

https://rise4fun.com/Alive/JXt

llvm-svn: 330003
2018-04-13 10:56:35 +00:00
Roman Lebedev
4275672d4a [InstCombine]: foldSelectICmpAndAnd(): and is commutative
Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.

I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]

This extends/generalizes that fold, so it is handled too.

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45539

llvm-svn: 330001
2018-04-13 09:57:57 +00:00
Sander de Smalen
5f8d1b87b5 [AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.
Summary:
Added Z_(b|h|s|d) vector list RegisterOperands along with support to
add/print the vector lists.

This is patch [5/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45431

llvm-svn: 330000
2018-04-13 09:11:53 +00:00
Gabor Buella
59f04da446 [X86] Introduce cldemote instruction
Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45256

llvm-svn: 329992
2018-04-13 07:35:08 +00:00
Martin Storsjo
c50e50418b [Support] Fix building for Windows on ARM
The commit in SVN r310001 that added support for this actually didn't
use the right struct field for the frame pointer - for ARM, there is
no register named Fp in the CONTEXT struct. On Windows, the R11
register is used as frame pointer.

Differential Revision: https://reviews.llvm.org/D45590

llvm-svn: 329991
2018-04-13 06:38:02 +00:00
Craig Topper
5f50d95003 [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.
This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.

We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.

llvm-svn: 329990
2018-04-13 06:07:18 +00:00
Yunlian Jiang
dfd7baa5a5 Enable debug fission for thinLTO linked via gold-plugin
Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user. 

Reviewers: tejohnson, pcc, dblaikie

Reviewed By: pcc

Subscribers: JDevlieghere, mehdi_amini, inglorion

Differential Revision: https://reviews.llvm.org/D44792

llvm-svn: 329988
2018-04-13 05:03:28 +00:00
Xin Tong
5f59365a73 [CallSiteSplit] Fix comment. NFC
llvm-svn: 329987
2018-04-13 04:35:38 +00:00
Erik Pilkington
da90ea4792 Fix another bot failure from r329951.
llvm-svn: 329986
2018-04-13 02:53:26 +00:00
Tony Tye
0a38435330 [AMDGPU] Update relocation record description
Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587

llvm-svn: 329981
2018-04-13 01:01:27 +00:00
Aaron Smith
9d297de1c9 [lit] Remove duplicate to_string method
There are two versions of to_string used by TestRunner.py. The one defined 
in TestRunner.py and the one defined in utils/lit/lit/util.py. The util.py
version is superior to the TestRunner.py version.

This change removes the duplicate to_string in TestRunner.py in favor of
always using the version from util.py. Beside removing duplicate code, this
makes it easier to debug TestRunner.py since only one version of to_string
is used.

Patch by Stella Stamenova!

llvm-svn: 329972
2018-04-12 23:45:15 +00:00
Simon Pilgrim
39d12c6fe3 [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.
Was being used to move around empty/unused itineraries...

llvm-svn: 329970
2018-04-12 22:57:34 +00:00
Erik Pilkington
1d3c67668c Free a pointer, fix a bot.
llvm-svn: 329969
2018-04-12 22:54:47 +00:00
Simon Pilgrim
4c267ba6eb [X86] Remove x86 InstrItinClass entries (PR37093)
This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093.

llvm-svn: 329967
2018-04-12 22:44:47 +00:00
Fangrui Song
bc99ced9a0 [CachePruning] Clarify the per-directory entry limit on Linux ext4.
Summary:
508   root node entries (root_limit)
510   internal node entries (node_limit)

For a filename with 40 bytes, its sizeof(ext4_dir_entry_2) = 48, a linear directory can contain at most floor(4096/48)=85 of them.
The real per-directory entry limit should be 508*510*85 = 22021800
The limit varies with the average length of filenames.

However, the Linux ext4 code does not try rebalancing the htree, so we will not be able to create filenames in a full leaf node. This is demonstrated with the following example, certain filenames cannot be used while others can:

  % touch d/0000000000000000000000000000000000816a6f
  touch: cannot touch 'd/0000000000000000000000000000000000816a6f': No
  space left on device
  % touch d/0000000000000000000000000000000000816a70
  # succeeded

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45546

llvm-svn: 329966
2018-04-12 22:27:38 +00:00
Sanjay Patel
b1fde3cede [DAGCombiner] simplify code; NFC
llvm-svn: 329964
2018-04-12 22:14:58 +00:00
Sanjay Patel
55786058ca [PowerPC] add fsub-fneg test; NFC
This is a test for a transform that was suggested in the post-commit
mailing list thread for rL329821. The target in question is not in
trunk, so PPC gets to stand in for it because it's the only in-tree
target that sets 'isFPExtFree()' to 'true'.

llvm-svn: 329963
2018-04-12 22:14:23 +00:00
Eli Friedman
012a4bfaa4 Don't call skipModule for CFI lowering passes.
opt-bisect shouldn't skip these passes; they lower intrinsics which
no other pass can handle.

llvm-svn: 329961
2018-04-12 22:04:11 +00:00
George Burgess IV
5e474b2be3 [ProfileSummary] Remove repeated cutoffs; NFCI
I'm told the repeat of "500000, 600000," is accidental, and should be
removed.

llvm-svn: 329959
2018-04-12 21:38:43 +00:00
Brian Gesiak
a53989e5a9 Let llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr
Summary:
llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr.
(This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`)

This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 .



Reviewers: dexonsmith, rjmccall

Reviewed By: rjmccall

Subscribers: chenwj, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D34856

llvm-svn: 329957
2018-04-12 21:28:04 +00:00
Peter Collingbourne
d59dff036b AArch64: Introduce a DAG combine for folding offsets into addresses.
This is a code size win in code that takes offseted addresses
frequently, such as C++ constructors that typically need to compute
an offseted address of a vtable. This reduces the size of Chromium
for Android's .text section by 108KB.

Differential Revision: https://reviews.llvm.org/D45199

llvm-svn: 329956
2018-04-12 21:23:55 +00:00
Vedant Kumar
5d0335a194 [DebugInfo] Create merged locations for instructions other than calls
This lifts a restriction on DILocation::getMergedLocation(), allowing it
to create merged locations for instructions other than calls.

Instruction::applyMergedLocation() now defaults to creating merged
locations for all instructions.

The default behavior of getMergedLocation() is unchanged: callers which
invoke it directly are unaffected.

This change will enable a follow-up Mem2Reg fix which improves crash
reporting.

Differential Revision: https://reviews.llvm.org/D45396

llvm-svn: 329955
2018-04-12 20:58:24 +00:00
George Burgess IV
433915c6fd [ProfileSummary] Move a vector we're about to destroy anyway; NFC
llvm-svn: 329954
2018-04-12 20:54:05 +00:00
Simon Pilgrim
1bf1fbc76a [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)
llvm-svn: 329953
2018-04-12 20:47:34 +00:00
Erik Pilkington
0491f0a0a5 [demangler] Add a partial demangling API for LLDB.
This parses a mangled name into an AST (typically an intermediate stage in
itaniumDemangle) and provides some functions to query certain properties or
print certain parts of the demangled name.

Differential revision: https://reviews.llvm.org/D44668

llvm-svn: 329951
2018-04-12 20:41:38 +00:00
Erik Pilkington
3fbc0e3d51 [demangler] NFC: Some refactoring to support partial demangling.
I'm committing this to libcxxabi too so that the two demanglers remain as
simular as possible.

llvm-svn: 329950
2018-04-12 20:41:06 +00:00
Sam Clegg
ba01f141a9 [WebAssembly] libObject: Don't include the name the size of custom sections
Differential Revision: https://reviews.llvm.org/D45579

llvm-svn: 329947
2018-04-12 20:31:12 +00:00
Simon Pilgrim
2bb15c54ea [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)
llvm-svn: 329945
2018-04-12 19:59:35 +00:00
Lang Hames
b5cbfae5ca [ORC] Use insert rather than emplace.
Hopefully this will fix the build failure at
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/9028

llvm-svn: 329944
2018-04-12 19:54:41 +00:00
George Burgess IV
01ed37787f Simplify; NFCI
llvm-svn: 329943
2018-04-12 19:48:05 +00:00
Simon Pilgrim
8a1fd6f25f [X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)
llvm-svn: 329940
2018-04-12 19:25:07 +00:00
Sameer AbuAsal
2ac010c054 [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

llvm-svn: 329939
2018-04-12 19:22:40 +00:00
Simon Pilgrim
3fe293ca40 [X86] Remove remaining gpr schedule itineraries (PR37093)
llvm-svn: 329938
2018-04-12 18:46:15 +00:00
Gabor Buella
556f5822bc [X86] Introduce LLVM wbinvd intrinsic
A previously missing intrinsic for an old instruction.

Reviewers: craig.topper, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45312

llvm-svn: 329936
2018-04-12 18:38:18 +00:00
George Burgess IV
36be8b4a1e Fix a typo in a comment; NFC
llvm-svn: 329935
2018-04-12 18:36:01 +00:00
Lang Hames
7a54926cb9 [ORC] Plumb error notifications through the VSO interface.
This allows materializers to notify the VSO that they were unable to
resolve or finalize symbols.

llvm-svn: 329934
2018-04-12 18:35:08 +00:00
Simon Pilgrim
42742ad477 [X86] Remove gpr shift/extension schedule itineraries (PR37093)
llvm-svn: 329933
2018-04-12 18:25:38 +00:00
Lei Huang
b4b69f9121 [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:

  * xscvsdqp
  * xscvudqp

Differential Revision: https://reviews.llvm.org/D45230

llvm-svn: 329931
2018-04-12 18:00:14 +00:00
Benjamin Kramer
edeedc5d9b [MCJIT] Remove the anchor from mcjit.
This is a layering violation. LTO shouldn't depend on MCJIT. The right
fix for this is moving the class somewhere else.

llvm-svn: 329929
2018-04-12 17:28:30 +00:00
Petar Jovanovic
5957118b20 [MIPS GlobalISel] remove superfluous #includes (NFC)
Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().

llvm-svn: 329926
2018-04-12 17:01:46 +00:00
Jessica Paquette
e52f1ef99a [AArch64] Move AFI->setRedZone(false) to top of emitPrologue
AFI->setRedZone(false) was put in the wrong place before, and so it only fired
on functions that didn't have stack frames. This moves that to the top of
emitPrologue to make sure that every function without a redzone has it set
correctly.

This also adds a function representing one of the early exit cases (GHC calling
convention) to the MachineOutliner noredzone test to ensure that we can outline
from functions like these, where we never use a redzone.

llvm-svn: 329922
2018-04-12 16:16:18 +00:00