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Commit Graph

131597 Commits

Author SHA1 Message Date
Daniel Sanders
202cd56665 [mips][ias] Correct ELF eflags when Octeon is the target.
Reviewers: sdardis

Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D18899

llvm-svn: 269283
2016-05-12 11:31:19 +00:00
Daniel Sanders
f64c0bb52e [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in needsRelocateWithSymbol()
Summary:
This eliminates the default case for N64 that was left out of r269047.

The change to R_MIPS_SUB is needed in this patch to make this testable since
%lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get
a compound relocation from the assembler.

Reviewers: sdardis, rafael

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20097

llvm-svn: 269280
2016-05-12 10:55:00 +00:00
Dan Gohman
fffd2940a1 [WebAssembly] Fast-isel support for calls, arguments, and selects.
llvm-svn: 269273
2016-05-12 04:19:09 +00:00
Hal Finkel
ff8397dabb [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTrunc
While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is
possible for one of the nodes to be replaced by another. To make sure we do not
visit the deleted nodes, and to make sure we visit the replacement nodes, use a
list of HandleSDNodes to track the to-be-promoted nodes during the promotion
process.

The same fix has been applied to the analogous code in
PPCTargetLowering::DAGCombineTruncBoolExt.

Fixes PR26985.

llvm-svn: 269272
2016-05-12 04:00:56 +00:00
David Majnemer
7230d61b65 [SCCP] Resolve shifts beyond the bitwidth to undef
Shifts beyond the bitwidth are undef but SCCP resolved them to zero.
Instead, DTRT and resolve them to undef.

This reimplements the transform which caused PR27712.

llvm-svn: 269269
2016-05-12 03:07:40 +00:00
Matt Arsenault
13446c4387 AMDGPU: Fix getIntegerAttribute type and error message
llvm-svn: 269268
2016-05-12 02:45:18 +00:00
Xinliang David Li
7d6d558b72 [Layout] Add a new test case for optimal rotation
Enabled by -force-precise-rotation-cost option

llvm-svn: 269267
2016-05-12 02:19:16 +00:00
Xinliang David Li
f70f3a4073 [Layout] Add a new option (NFC)
Currently cost based loop rotation algo can only be turned on with
two conditions: the function has real profile data, and -precise-rotation-cost
flag is turned on. This is not convenient for developers to experiment
when profile is not available. Add a new option to force the new
rotation algorithm -force-precise-rotation-cost

llvm-svn: 269266
2016-05-12 02:04:41 +00:00
Matt Arsenault
ac3313688f AMDGPU: Fix breaking IR on instructions with multiple pointer operands
The promote alloca pass would attempt to promote an alloca with
a select, icmp, or phi user, even though the other operand was
from a non-promotable source, producing a select on two different
pointer types.

Only do this if we know that both operands derive from the same
alloca. In the future we should be able to relax this to an alloca
which will also be promoted.

llvm-svn: 269265
2016-05-12 01:58:58 +00:00
Chris Bieneman
ed41711e86 [obj2yaml] Adding Error/Expected to macho2yaml
I figure if I'm adding Mach support I may as well use the new fancy Error model.

llvm-svn: 269264
2016-05-12 01:52:33 +00:00
Chad Rosier
95d924439b [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.
llvm-svn: 269263
2016-05-12 01:42:01 +00:00
Sanjoy Das
e760f15e56 Appease MSVC with curly braces
llvm-svn: 269262
2016-05-12 01:38:08 +00:00
Sanjoy Das
ee178ad6c3 All llvm.deoptimize declarations must use the same calling convention
This new verifier rule lets us unambigously pick a calling convention
when creating a new declaration for
`@llvm.experimental.deoptimize.<ty>`.  It is also congruent with our
lowering strategy -- since all calls to `@llvm.experimental.deoptimize`
are lowered to calls to `__llvm_deoptimize`, it is reasonable to enforce
a unique calling convention.

Some of the tests that were breaking this verifier rule have had to be
split up into different .ll files.

The inliner was violating this rule as well, and has been fixed to avoid
producing invalid IR.

llvm-svn: 269261
2016-05-12 01:17:38 +00:00
Chad Rosier
6c16f1042e [AArch64] Remove floating-point narrow stores from getUsefulBitsForUse.
While not impossible, it's unlikely we'd be performing bitwise operations on FP
values.

llvm-svn: 269260
2016-05-12 01:04:15 +00:00
Justin Bogner
8b8b978841 SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISel
This is a large change, but it's pretty mechanical:
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

llvm-svn: 269258
2016-05-12 00:31:09 +00:00
Justin Bogner
7757871659 SDAG: Clean up dangling nodes in ARMISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

llvm-svn: 269256
2016-05-12 00:20:19 +00:00
Xinliang David Li
9f553a03a3 [profile] profile writing cleanup
Do not precompute value counts for all sites. This 
eliminates one more use of dynamic allocation 
in profiler writer.

llvm-svn: 269253
2016-05-11 23:21:12 +00:00
Davide Italiano
9c6851f574 Revert "[SCCP] Partially propagate informations when the input is not fully defined."
This reverts commit r269105 as it caused PR27712.

llvm-svn: 269252
2016-05-11 23:06:10 +00:00
Teresa Johnson
9f75184a1e [ThinLTO] Don't re-analyze callee at same threshold unnecessarily
This should just be a compile-time change. Correct the check for whether
we have already analyzed the callee when making summary based decisions.
There is no need to reprocess one at the same threshold as when it was
last processed.

llvm-svn: 269251
2016-05-11 22:56:19 +00:00
Wei Mi
c43ebe58f1 Fix a bug when hoist spill to a BB with landingpad successor.
This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612.

When spill is hoisted to a BB with landingpad successor, and if the VNI
of the spill reg lives into the landingpad successor, the spill should be
inserted before the call which may throw exception. InsertPointAnalysis
is used to compute the safe insert point.

http://reviews.llvm.org/D20027 is a preparing patch for this patch.

Differential Revision: http://reviews.llvm.org/D19884.

llvm-svn: 269249
2016-05-11 22:37:43 +00:00
Wei Mi
ee383d9f9c [NFC] Extract LastSplitPoint computation from SplitAnalysis to a new class
InsertPointAnalysis.

Because both split and spill hoisting want to use LastSplitPoint computation
result, extract the LastSplitPoint computation from SplitAnalysis class which
also contains a bunch of other analysises only related to split.

Differential Revision: http://reviews.llvm.org/D20027.

llvm-svn: 269248
2016-05-11 22:28:29 +00:00
Justin Bogner
b8461809ec SDAG: Use ReplaceNode here, not ReplaceUses
This was a typo in an earlier commit - there's no point in keeping the
old node around here.

Noticed by Meador Inge. Thanks!

llvm-svn: 269245
2016-05-11 22:21:50 +00:00
Chris Bieneman
7ae0bc028f Initial add for MachO support for yaml2obj
Adding the initial files for adding MachO support to yaml2obj. Passing a MachO file will result in an error.

I will be implementing obj2yaml and yaml2obj for MachO in parallel so that one can be used to test the other.

llvm-svn: 269244
2016-05-11 22:07:48 +00:00
Chris Bieneman
80178ca710 Initial add for MachO support for obj2yaml
Adding the initial files for adding MachO support to obj2yaml. Passing a MachO file will result in a new not_implemented error.

I will be implementing obj2yaml and yaml2obj for MachO in parallel so that one can be used to test the other.

llvm-svn: 269243
2016-05-11 22:07:45 +00:00
Sanjay Patel
05127ecda9 regenerate checks
llvm-svn: 269241
2016-05-11 21:51:28 +00:00
Matthias Braun
8286e89a06 MachineVerifier: Fix error reporting.
Do not use getVRegDef() to print "the definition" of a vreg. If there
are multiple or none the function will fail.

llvm-svn: 269239
2016-05-11 21:31:39 +00:00
Xinliang David Li
cadd519e8b cleanup: do not recompute size for preallocated buffer
llvm-svn: 269238
2016-05-11 21:17:10 +00:00
Justin Bogner
68015d402f SDAG: Add a helper to replace and remove a node during ISel
It's very common to want to replace a node and then remove it since
it's dead, especially as we port backends from the SDNode *Select API
to the void Select one. This helper makes this sequence a bit less
verbose.

llvm-svn: 269236
2016-05-11 21:13:17 +00:00
Justin Bogner
07dae12a03 SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a node
It's awkward to force callers of SelectNodeTo to figure out whether
the node was morphed or CSE'd. Update uses here instead of requiring
callers to (sometimes) do it.

llvm-svn: 269235
2016-05-11 21:00:33 +00:00
Teresa Johnson
8a23fb7cb0 [ThinLTO] Fix Windows debug failure in new iterator
This fixes a debug assert on Windows from the new iterator
implementation added in r269059. The Windows std::vector iterator
operator== checks in debug mode that the containers being iterated over
are the same, which they may not be.

Fixed by checking that we are iterating over the same container before
comparing the container iterators.

llvm-svn: 269232
2016-05-11 20:46:22 +00:00
Chad Rosier
f28ce785a9 [AArch64] Improve getUsefulBitsForUse for narrow stores.
For narrow stores (e.g., strb, srth) we know the upper bits of the register are
unused/not useful. In some cases we can use this information to eliminate
unnecessary instructions.

For example, without this patch we generate (from the 2nd test case):

 ldr w8, [x0]
 and w8, w8, #0xfff0
 bfxil w8, w2, #16, #4
 strh w8, [x1]

and after the patch the 'and' is removed:

 ldr w8, [x0]
 bfxil w8, w2, #16, #4
 strh w8, [x1]
 ret

During the lowering of the bitfield insert instruction the 'and' is eliminated
because we know the upper 16-bits that are masked off are unused and the lower
4-bits that are masked off are overwritten by the insert itself. Therefore, the
'and' is unnecessary.

Differential Revision: http://reviews.llvm.org/D20175

llvm-svn: 269226
2016-05-11 20:19:54 +00:00
Sanjay Patel
c6e7e8a753 fix documentation comments; NFC
llvm-svn: 269225
2016-05-11 20:10:33 +00:00
Vedant Kumar
0b388cc75a [ProfileData] Use SoftInstrProfErrors to count soft errors, NFC
Differential Revision: http://reviews.llvm.org/D20082

llvm-svn: 269222
2016-05-11 19:42:19 +00:00
Simon Pilgrim
a3413342cc [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.
Fixed incorrect operands indices used to access src registers

llvm-svn: 269221
2016-05-11 18:53:44 +00:00
Rafael Espindola
e34ff25d67 Return a StringRef from getSection.
This is similar to how getName is handled.

llvm-svn: 269218
2016-05-11 18:21:59 +00:00
Zachary Turner
e4678c41e6 Fix build breakage in DebugInfoCodeview
llvm-svn: 269217
2016-05-11 17:54:20 +00:00
Zachary Turner
cb79b018ec Refactor CodeView type records to use common code.
Differential Revision: http://reviews.llvm.org/D20138
Reviewed By: rnk

llvm-svn: 269216
2016-05-11 17:47:35 +00:00
Justin Bogner
92653db343 SDAG: Minor cleanup in X86
Don't bother returning a result we don't use here. I've also renamed
this from selectGather to tryGather to better indicate that it may not
do anything.

llvm-svn: 269215
2016-05-11 17:46:03 +00:00
Sanjoy Das
3f12ce1fd4 [SCEVExpander] Fix a failed cast<> assertion
SCEVExpander::replaceCongruentIVs assumes the backedge value of an
SCEV-analysable PHI to always be an instruction, when this is not
necessarily true.  For now address this by bailing out of the
optimization if the backedge value of the PHI is a non-Instruction.

llvm-svn: 269213
2016-05-11 17:41:41 +00:00
Sanjoy Das
cb6b35a484 [SCEVExpander] Don't break SSA in replaceCongruentIVs
`SCEVExpander::replaceCongruentIVs` bypasses `hoistIVInc` if both the
original and the isomorphic increments are PHI nodes.  Doing this can
break SSA if the isomorphic increment is not dominated by the original
increment.  Get rid of the bypass, and let `hoistIVInc` do the right
thing.

Fixes PR27232 (compile time crash/hang).

llvm-svn: 269212
2016-05-11 17:41:34 +00:00
Sanjoy Das
8c40c5bf03 [SCEV] Be more aggressive around proving no-wrap
... for AddRec's in loops for which SCEV is unable to compute a max
tripcount.  This is not a problem for "normal" loops[0] that don't have
guards or assumes, but helps in cases where we have guards or assumes in
the loop that can be used to constrain incoming values over the backedge.

This partially fixes PR27691 (we still don't handle the NUW case).

[0]: for "normal" loops, in the cases where we'd be able to prove
no-wrap via isKnownPredicate, we'd also be able to compute a max
tripcount.

llvm-svn: 269211
2016-05-11 17:41:26 +00:00
Simon Pilgrim
2806445322 [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.
llvm-svn: 269209
2016-05-11 17:36:32 +00:00
Jan Vesely
6b5644eeff AMDGPU: Split private memory tests
Reenable R600 testing

reviewer: arsenm

Differential Revision: http://reviews.llvm.org/D20031

llvm-svn: 269207
2016-05-11 17:24:45 +00:00
Sanjay Patel
cc684634d9 fix typos in comments; NFC
llvm-svn: 269206
2016-05-11 17:00:07 +00:00
Filipe Cabecinhas
73a19911a5 [NFC] Remove some dead code:
DbgInfoIntrinsic::StripCast() is dead since r79977
The only function that creates Comdat objects seems to be in Module, and always creates them using the default constructor.

llvm-svn: 269204
2016-05-11 16:38:40 +00:00
Dan Gohman
7445a2e54f [WebAssembl] Implement enough of fast-isel to run the comparison tests.
llvm-svn: 269203
2016-05-11 16:32:42 +00:00
Vedant Kumar
a39c891e7e Use an emplace_back for consistency, NFC
llvm-svn: 269199
2016-05-11 16:03:02 +00:00
Vedant Kumar
641c55ebd0 [BasicAA] Compare GEP indices based on value (Fix PR27418)
Equivalent GEP indices with different types are treated as different
indices altogether, leading to an incorrect AA result. Fix the issue
by comparing indices based on their values.

Thanks to Mikael Holmén for reporting the issue!

Differential Revision: http://reviews.llvm.org/D19935

llvm-svn: 269197
2016-05-11 15:45:43 +00:00
Daniel Sanders
b13f3435de [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by r268900
microMIPS has a special case that is not correctly implemented in LLVM. If we
have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an
R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The
in-place addend should therefore be 0x11.

Work around this by partially reverting the effect of r268900 by keeping the
symbol when the STO_MIPS_MICROMIPS flag is set. This fixes
SingleSource/Regression/C/PR640 for microMIPS.

llvm-svn: 269196
2016-05-11 15:44:23 +00:00
Simon Pilgrim
ea061f0a69 [X86][AVX512] Regenerate intrinsics test
llvm-svn: 269193
2016-05-11 15:13:29 +00:00