Dan Gohman
74529a2226
Split foldMemoryOperand into public non-virtual and protected virtual
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parts, and add target-independent code to add/preserve
MachineMemOperands.
llvm-svn: 60488
2008-12-03 18:43:12 +00:00
Dan Gohman
04e99d0f3f
Add more const qualifiers. This fixes build breakage from r59540.
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llvm-svn: 59542
2008-11-18 19:49:32 +00:00
Evan Cheng
b3fd30ed7c
Minor code restructuring. No functionality change.
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llvm-svn: 58643
2008-11-03 21:02:39 +00:00
Dan Gohman
86527c1834
Const-ify several TargetInstrInfo methods.
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llvm-svn: 57622
2008-10-16 01:49:15 +00:00
Dan Gohman
30c5ce1b7d
Switch the MachineOperand accessors back to the short names like
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isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
Owen Anderson
5fef19facf
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
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was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Owen Anderson
600a8ca0d5
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
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llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Dan Gohman
cd25487258
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Evan Cheng
1f6148a84c
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
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- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
llvm-svn: 53097
2008-07-03 09:09:37 +00:00
Owen Anderson
604f9f722d
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
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Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Dan Gohman
c8097f8c8c
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
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the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Nicolas Geoffray
82baa2d2c6
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
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llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng
38a755499d
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
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llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Chris Lattner
49e9edd6f6
Fix "Control reaches the end of non-void function" warnings,
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patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
Evan Cheng
11d2c09adc
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Evan Cheng
18064ddb5b
Refactor code. Remove duplicated functions that basically do the same thing as
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findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
Dan Gohman
cabaec582f
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng
90f03a0b88
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
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llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Owen Anderson
946d55e773
Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead.
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llvm-svn: 46016
2008-01-15 22:02:46 +00:00
Chris Lattner
0293fca6d8
rename MachineInstr::setInstrDescriptor -> setDesc
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llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Evan Cheng
9de4f35e9f
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
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llvm-svn: 45727
2008-01-07 23:56:57 +00:00
Chris Lattner
f83aae613c
rename TargetInstrDescriptor -> TargetInstrDesc.
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Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner
57e851edfe
Rename all the M_* flags to be namespace qualified enums, and switch
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all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
llvm-svn: 45692
2008-01-07 06:42:05 +00:00
Chris Lattner
9d38dfa4a5
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
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llvm-svn: 45680
2008-01-07 03:13:06 +00:00
Chris Lattner
55343065e3
remove MachineOpCode typedef.
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llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Chris Lattner
f7f96d818f
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
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that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Owen Anderson
f19692b2f6
Move even more functionality from MRegisterInfo into TargetInstrInfo.
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Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Chris Lattner
14310afe42
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Owen Anderson
2adf8c5533
Move some more functionality from MRegisterInfo to TargetInstrInfo.
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llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Owen Anderson
e6856128ab
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
1285ec2ae7
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
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a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
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Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
9e5cc35593
Add new shorter predicates for testing machine operands for various types:
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e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
12477d46b4
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
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llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner
fac8748ca7
use simplified operand addition methods.
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llvm-svn: 45437
2007-12-30 01:01:54 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Dan Gohman
fb60c0dfed
Remove isReg, isImm, and isMBB, and change all their users to use
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isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
Owen Anderson
4b71e55287
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
Dale Johannesen
eb2c2823e3
ARM: make branch folder remove unconditional branches
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following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
llvm-svn: 39782
2007-07-12 16:45:35 +00:00
Evan Cheng
abcf3842bb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng
92e624a6f7
Incorrect check.
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llvm-svn: 37962
2007-07-06 23:23:19 +00:00
Evan Cheng
be54fdf431
Reflects the chanegs made to PredicateOperand.
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llvm-svn: 37898
2007-07-05 07:18:20 +00:00
Dan Gohman
9cbc3fb1ab
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng
e6d0631c68
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
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llvm-svn: 37606
2007-06-15 21:15:00 +00:00
Dale Johannesen
7e3253f115
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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llvm-svn: 37571
2007-06-13 17:59:52 +00:00
Evan Cheng
1a6c0341fd
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
Evan Cheng
4c6df8ba37
Fix ARM condition code subsumission check.
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llvm-svn: 37517
2007-06-08 09:14:47 +00:00
Evan Cheng
9f23724d53
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
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llvm-svn: 37484
2007-06-07 01:37:54 +00:00
Evan Cheng
ff31eed2be
Add missing const qualifiers.
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llvm-svn: 37342
2007-05-29 18:42:18 +00:00
Evan Cheng
80122ab529
Hooks for predication support.
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llvm-svn: 37308
2007-05-23 07:22:05 +00:00
Evan Cheng
f448047ec2
Fix some -march=thumb regressions. tBR_JTr is not predicable.
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llvm-svn: 37272
2007-05-21 23:17:32 +00:00
Evan Cheng
d173398eee
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
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llvm-svn: 37268
2007-05-21 18:56:31 +00:00
Evan Cheng
90b0ff05f6
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Evan Cheng
973f4a19cb
PredicateInstruction returns true if the operation was successful.
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llvm-svn: 37124
2007-05-16 21:53:07 +00:00
Evan Cheng
f7a017dfa7
Removed isPredicable().
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llvm-svn: 37119
2007-05-16 20:50:23 +00:00
Evan Cheng
34928ae31f
Hooks for predication support.
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llvm-svn: 37093
2007-05-16 02:01:49 +00:00
Evan Cheng
9f0ffdf4b3
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Dale Johannesen
7c3b78cf98
Rewrite of Thumb constant islands handling (exact allowance for padding
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around islands and jump tables).
llvm-svn: 36573
2007-04-29 19:19:30 +00:00
Evan Cheng
eff332e3e1
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
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llvm-svn: 36483
2007-04-26 19:00:32 +00:00
Evan Cheng
de9468373e
Relex assertions to account for additional implicit def / use operands.
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llvm-svn: 36430
2007-04-25 07:12:14 +00:00
Anton Korobeynikov
f3e62a428a
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
Evan Cheng
16696f0ad8
Inverted logic.
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llvm-svn: 35619
2007-04-03 06:44:25 +00:00
Evan Cheng
968135bd3f
findRegisterUseOperand() changed.
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llvm-svn: 35366
2007-03-26 22:41:48 +00:00
Evan Cheng
8d374caead
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
60bde0ebb1
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
Evan Cheng
5e0f0364d0
Copy and paste bug.
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llvm-svn: 33658
2007-01-30 08:22:33 +00:00
Evan Cheng
78628c7f32
Misseed thumb jumptable branch.
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llvm-svn: 33656
2007-01-30 08:03:06 +00:00
Evan Cheng
171943e26e
Factor GetInstSize() out of constpool island pass.
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llvm-svn: 33644
2007-01-29 23:45:17 +00:00
Jim Laskey
23ed7d2625
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng
c6e1d453d3
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Evan Cheng
98fa7ab4d7
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Rafael Espindola
2259fab5cf
fix warning about missing newline at end of file
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llvm-svn: 31162
2006-10-24 17:07:11 +00:00
Chris Lattner
71dc932fcb
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
Rafael Espindola
1a3020bfcf
add shifts to addressing mode 1
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llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Rafael Espindola
89ac048c5d
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola
ae2d1c53c7
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola
bb1e2e2c52
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00