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2112a6d7b8
Commit Graph

465 Commits

Author SHA1 Message Date
Chris Lattner
2112a6d7b8 Remove implicit information from instruction selector 
llvm-svn: 4811
 2002-11-21 18:54:29 +00:00
Chris Lattner
c9e824d750 Add printing information for MUL and DIV 
llvm-svn: 4810
 2002-11-21 18:54:14 +00:00
Chris Lattner
d2207d5464 Fix a bug that prevented compilation of multiple functions 
llvm-svn: 4809
 2002-11-21 17:26:58 +00:00
Chris Lattner
fab5468d86 Remove opcode information for instructions that are completely defined now 
llvm-svn: 4805
 2002-11-21 17:12:55 +00:00
Chris Lattner
d432d2f75e Add printing support for sahf & setcc 
llvm-svn: 4804
 2002-11-21 17:10:57 +00:00
Chris Lattner
766d0da035 Add printing support for /0 /1 type instructions 
llvm-svn: 4803
 2002-11-21 17:09:01 +00:00
Chris Lattner
9f9d6aef08 Add support for /0 /1, etc type instructions 
llvm-svn: 4802
 2002-11-21 17:08:49 +00:00
Chris Lattner
b1b5855551 Rename the SetCC X86 instructions to reflect the fact that they are the 
register versions

llvm-svn: 4800
 2002-11-21 16:19:42 +00:00
Chris Lattner
d6236d8100 Simplify setcc code a bit 
llvm-svn: 4799
 2002-11-21 15:52:38 +00:00
Chris Lattner
2f9488d131 Support Registers of the form (B8+ rd) for example 
llvm-svn: 4798
 2002-11-21 02:00:20 +00:00
Chris Lattner
32bfb6a115 Dont' set flags 
llvm-svn: 4797
 2002-11-21 01:59:50 +00:00
Chris Lattner
aa8aa73902 Implement printing more, implement opcode output more 
llvm-svn: 4796
 2002-11-21 01:33:44 +00:00
Chris Lattner
53a9c9aac6 Huge diff do to reindeinting comments. 
Basically just adds OpSize flags for instructions that need them.

llvm-svn: 4795
 2002-11-21 01:33:28 +00:00
Chris Lattner
92a3c2c77d Add new prefix flag 
llvm-svn: 4794
 2002-11-21 01:32:55 +00:00
Chris Lattner
228180c2ae Print another class of instructions correctly, giving us: xorl EDX, EDX 
for example.

llvm-svn: 4793
 2002-11-21 00:30:01 +00:00
Misha Brukman
5d89dbcf41 Booleans are types too. And they get stored in bytes. And InstructionSelection 
doesn't assert fail. And everyone's happy. Yay!

llvm-svn: 4792
 2002-11-21 00:25:56 +00:00
Chris Lattner
26052792dd X86 target builds fine now 
llvm-svn: 4786
 2002-11-20 20:17:03 +00:00
Misha Brukman
96283090dc Add definitions for function headers from MRegisterInfo.h: 
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

llvm-svn: 4784
 2002-11-20 18:59:43 +00:00
Misha Brukman
42f51b24e1 Check not only for MO_VirtualRegister, but MO_MachineRegister as well when 
printing out assembly. After all, we want the real thing too.

llvm-svn: 4783
 2002-11-20 18:56:41 +00:00
Chris Lattner
2f7f21cd13 Don't build X86 target yet 
llvm-svn: 4780
 2002-11-20 18:37:37 +00:00
Misha Brukman
505ca2e419 Add mapping in MachineFunction from SSA regs to Register Classes. Also, 
uncovered a bug where registers were not being put in a map if they were not
found...

llvm-svn: 4776
 2002-11-20 00:58:23 +00:00
Misha Brukman
8d3bef2e1b Sigh. Fixed some speling. 
llvm-svn: 4775
 2002-11-20 00:56:42 +00:00
Misha Brukman
00d8343760 Thanks to the R8, R16, and R32 macros, I can now deal with registers that 
belong to different register classes easier.

llvm-svn: 4773
 2002-11-20 00:47:40 +00:00
Brian Gaeke
49acd3c0ba Brian Gaeke says: 
lib/Target/X86/InstSelectSimple.cpp: Add a little something to
 visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8

llvm-svn: 4755
 2002-11-19 09:08:47 +00:00
Chris Lattner
cd1f56fc36 Start trying to print instructions more correctly. For now we also print out the opcode for each instruction as well. 
llvm-svn: 4743
 2002-11-18 06:56:51 +00:00
Chris Lattner
8301d751ee Expose base opcode 
llvm-svn: 4742
 2002-11-18 06:56:24 +00:00
Chris Lattner
54bb9d64a3 Start to add more information to instr.def 
llvm-svn: 4741
 2002-11-18 05:37:11 +00:00
Chris Lattner
e921369cf7 Add instruction annotation about whether it has a 0x0F opcode prefix 
llvm-svn: 4740
 2002-11-18 01:59:28 +00:00
Chris Lattner
acf38562df Add more void flags 
llvm-svn: 4739
 2002-11-18 01:37:48 +00:00
Chris Lattner
7a67557e29 Set the void flag on instructions that should get it 
llvm-svn: 4738
 2002-11-18 01:34:36 +00:00
Chris Lattner
f0a1010d2c Pass on a targetmachine 
llvm-svn: 4736
 2002-11-17 23:22:03 +00:00
Chris Lattner
a7d7b16161 Arrange to have a TargetMachine available in X86InstrInfo::print 
llvm-svn: 4734
 2002-11-17 23:20:37 +00:00
Chris Lattner
700e8f6a01 Wow, I'm incapable of the simplest things today... 
llvm-svn: 4732
 2002-11-17 23:05:21 +00:00
Chris Lattner
1cd77c9933 Rename registers to follow the intel style of all caps 
llvm-svn: 4731
 2002-11-17 23:03:46 +00:00
Chris Lattner
0bf125c617 Fix misleading indentation 
llvm-svn: 4730
 2002-11-17 22:57:23 +00:00
Chris Lattner
5374a3be97 Reorganize printing interface a bit 
llvm-svn: 4728
 2002-11-17 22:53:13 +00:00
Chris Lattner
a55e8dba9b Add default implementation of printing interface 
llvm-svn: 4727
 2002-11-17 22:53:03 +00:00
Chris Lattner
970ae6d569 Fix minor detail 
llvm-svn: 4725
 2002-11-17 22:33:26 +00:00
Chris Lattner
72e99c8344 Fix Mul/Div clobbers 
llvm-svn: 4718
 2002-11-17 21:56:38 +00:00
Chris Lattner
dcb6f1dbf9 Fix a few typos, implement load/store 
llvm-svn: 4716
 2002-11-17 21:11:55 +00:00
Chris Lattner
06066e17c3 Add functions to buld X86 specific constructs 
llvm-svn: 4714
 2002-11-17 21:03:35 +00:00
Chris Lattner
5e21732045 Add information about memory index representation 
llvm-svn: 4712
 2002-11-17 20:33:26 +00:00
Chris Lattner
99b5e2f073 Add load/store instructions 
llvm-svn: 4711
 2002-11-17 20:33:12 +00:00
Chris Lattner
fb67938381 Switch visitRet to use getClass() 
llvm-svn: 4710
 2002-11-17 20:07:45 +00:00
Brian Gaeke
492e05ba01 include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline 
convenience method.  Fix typo in comment.
lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses.
 Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions.
 Take out LEAVE instructions.
 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo).
 Fix typo in comment and remove some FIXME comments.
lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h.
 Add some simple code to Printer::runOnFunction to iterate over
  MachineBasicBlocks and call X86InstrInfo::print().
lib/Target/X86/X86InstrInfo.def: Make some more instructions with
 implicit defs "Void".  Add more sign/zero extending "move" insns
 (movsx, movzx).
lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register.

llvm-svn: 4707
 2002-11-14 22:32:30 +00:00
Brian Gaeke
8cfe5d95f1 InstSelectSimple.cpp: (visitReturnInst) Add return instructions with return 
values.
X86InstrInfo.def: add LEAVE instruction.

llvm-svn: 4691
 2002-11-11 19:37:09 +00:00
Brian Gaeke
100510d2a8 Add instruction selection code and tests for setcc instructions 
llvm-svn: 4603
 2002-11-07 17:59:21 +00:00
Vikram S. Adve
51aa205bd1 Remove a nasty little semi-colon someone introduced which 
prevented any machine instrs from being printed!

llvm-svn: 4557
 2002-11-06 00:34:26 +00:00
Chris Lattner
79296d7609 Implement signed and unsigned division and remainder 
llvm-svn: 4508
 2002-11-02 20:54:46 +00:00
Chris Lattner
234cc2848a Implement multiply operator 
llvm-svn: 4506
 2002-11-02 20:28:58 +00:00