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Commit Graph

120876 Commits

Author SHA1 Message Date
Matt Arsenault
2211a78780 AMDGPU: Use DFS to avoid second loop over function
llvm-svn: 245772
2015-08-22 00:43:38 +00:00
Matt Arsenault
c8ff6e4f0e AMDGPU: Make sure to run verifier after SIFixSGPRLiveRanges
llvm-svn: 245769
2015-08-22 00:19:34 +00:00
Matt Arsenault
12b207c6f3 AMDGPU: Improve debug printing in SIFixSGPRLiveRanges
llvm-svn: 245768
2015-08-22 00:19:25 +00:00
Matt Arsenault
d80c9718c1 AMDGPU: Move CI instructions into CIInstructions.td
There are still a couple of CI patterns left in SIInstructions.

llvm-svn: 245767
2015-08-22 00:16:34 +00:00
Matt Arsenault
30e4b51f0a AMDGPU: Minor cleanups to help with f16 support
The main change is inverting the condition for the
operand class classes so that VT.Size == 16 uses VGPR_32
instead of 64.

llvm-svn: 245764
2015-08-21 23:49:51 +00:00
JF Bastien
91f6300e91 Improve the determinism of MergeFunctions
Summary:

Merge functions previously relied on unsigned comparisons of pointer values to
order functions. This caused observable non-determinism in the compiler for
large bitcode programs. Basically, opt -mergefuncs program.bc | md5sum produces
different hashes when run repeatedly on the same machine. Differing output was
observed on three large bitcodes, but it was less frequent on the smallest file.
It is possible that this only manifests on the large inputs, hence remaining
undetected until now.

This patch fixes this by removing (almost, see below) all places where
comparisons between pointers are used to order functions. Most of these changes
are local, but the comparison of global values requires assigning an identifier
to each local in the order it is visited. This is very similar to the way the
comparison function identifies Value*'s defined within a function. Because the
order of visiting the functions and their subparts is deterministic, the
identifiers assigned to the globals will be as well, and the order of functions
will be deterministic.

With these changes, there is no more observed non-determinism. There is also
only minor slowdowns (negligible to 4%) compared to the baseline, which is
likely a result of the fact that global comparisons involve hash lookups and not
just pointer comparisons.

The one caveat so far is that programs containing BlockAddress constants can
still be non-deterministic. It is not clear what the right solution is here. In
particular, even if the global numbers are used to order by function, we still
need a way to order the BasicBlock*'s. Unfortunately, we cannot just bail out
and fail to order the functions or consider them equal, because we require a
total order over functions. Note that programs with BlockAddress constants are
relatively rare, so the impact of leaving this in is minor as long as this pass
is opt-in.

Author: jrkoenig

Reviewers: nlewycky, jfb, dschuff

Subscribers: jevinskie, llvm-commits, chapuni

Differential revision: http://reviews.llvm.org/D12168

llvm-svn: 245762
2015-08-21 23:27:24 +00:00
Adam Nemet
40fc6ceb9d [LAA] Hold bounds via ValueHandles during SCEV expansion
SCEV expansion can invalidate previously expanded values.  For example
in SCEVExpander::ReuseOrCreateCast, if we already have the requested
cast value but it's not at the desired location, a new cast is inserted
and the old cast will be invalidated.

Therefore, when expanding the bounds for the pointers, a later entry can
invalidate the IR value for an earlier one.  The fix is to store a value
handle rather than the value itself.

The newly added test has a more detailed description of how the bug
triggers.

This bug can have a negative but potentially highly variable performance
impact in Loop Distribution.  Because one of the bound values was
invalidated and is an undef expression now, InstCombine is free to
transform the array overlap check:

   Start0 <= End1 && Start1 <= End0

into:

   Start0 <= End1

So depending on the runtime location of the arrays, we would detect a
conflict and fall back on the original loop of the versioned loop.

Also tested compile time with SPEC2006 LTO bc files.

llvm-svn: 245760
2015-08-21 23:19:57 +00:00
Tyler Nowicki
0df99a252e Standardized 'failed' to 'Failed' in LoopVectorizationRequirements.
llvm-svn: 245759
2015-08-21 23:03:24 +00:00
Alex Lorenz
c757bb60d6 MIRLangRef: Add 'MIR Testing Guide' section.
llvm-svn: 245757
2015-08-21 22:58:33 +00:00
Peter Collingbourne
db573c5328 LTO: Change signature of LTOCodeGenerator::setCodePICModel() to take a Reloc::Model.
This allows us to remove a bunch of code in LTOCodeGenerator and llvm-lto
and has the side effect of improving error handling in the libLTO C API.

llvm-svn: 245756
2015-08-21 22:57:17 +00:00
Tom Stellard
c3f6130f41 AMDGPU/SI: Better handle s_wait insertion
We can wait on either VM, EXP or LGKM.
The waits are independent.

Without this patch, a wait inserted because of one of them
would also wait for all the previous others.
This patch makes s_wait only wait for the ones we need for the next
instruction.

Here's an example of subtle perf reduction this patch solves:

This is without the patch:

buffer_load_format_xyzw v[8:11], v0, s[44:47], 0 idxen
buffer_load_format_xyzw v[12:15], v0, s[48:51], 0 idxen
s_load_dwordx4 s[44:47], s[8:9], 0xc
s_waitcnt lgkmcnt(0)
buffer_load_format_xyzw v[16:19], v0, s[52:55], 0 idxen
s_load_dwordx4 s[48:51], s[8:9], 0x10
s_waitcnt vmcnt(1)
buffer_load_format_xyzw v[20:23], v0, s[44:47], 0 idxen

The s_waitcnt vmcnt(1) is useless.
The reason it is added is because the last
buffer_load_format_xyzw needs s[44:47], which was issued
by the first s_load_dwordx4. It waits for all VM
before that call to have finished.

Internally after every instruction, 3 counters (for VM, EXP and LGTM)
are updated after every instruction. For example buffer_load_format_xyzw
will
increase the VM counter, and s_load_dwordx4 the LGKM one.

Without the patch, for every defined register,
the current 3 counters are stored, and are used to know
how long to wait when an instruction needs the register.

Because of that, the s[44:47] counter includes that to use the register
you need to wait for the previous buffer_load_format_xyzw.

Instead this patch stores only the counters that matter for the
register,
and puts zero for the other ones, since we don't need any wait for them.

Patch by: Axel Davy

Differential Revision: http://reviews.llvm.org/D11883

llvm-svn: 245755
2015-08-21 22:47:27 +00:00
Sanjoy Das
ead6e3fe61 Re-apply r245635, "[InstCombine] Transform A & (L - 1) u< L --> L != 0"
The original checkin was buggy, this change has a fix.

Original commit message:

[InstCombine] Transform A & (L - 1) u< L --> L != 0

Summary:

This transform is never a pessimization at the IR level (since it
replaces an `icmp` with another), and has potentiall payoffs:

 1. It may make the `icmp` fold away or become loop invariant.
 2. It may make the `A & (L - 1)` computation dead.

This shows up in Java, in range checks generated by array accesses of
the form `a[i & (a.length - 1)]`.

Reviewers: reames, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12210

llvm-svn: 245753
2015-08-21 22:22:37 +00:00
David Blaikie
9b832d73d7 Range-for-ify some things in GlobalMerge
llvm-svn: 245752
2015-08-21 22:19:06 +00:00
David Blaikie
bdffc32d98 [opaque pointer types] Fix a few easy places in GlobalMerge that were accessing value types through pointee types
llvm-svn: 245746
2015-08-21 22:00:44 +00:00
Alex Lorenz
fd8e770627 MIR Serialization: Serialize the pointer IR expression values in the machine
memory operands.

llvm-svn: 245745
2015-08-21 21:54:12 +00:00
Vedant Kumar
5213c133c7 [ARM] Fix MachO CPU Subtype selection
Differential Revision: http://reviews.llvm.org/D12040

llvm-svn: 245744
2015-08-21 21:52:48 +00:00
Alex Lorenz
58c9b18bbf MIRParser: Split the 'parseIRConstant' method into two methods. NFC.
One variant of this method can be reused when parsing the quoted IR pointer
expressions in the machine memory operands.

llvm-svn: 245743
2015-08-21 21:48:22 +00:00
David Blaikie
a1c619f61c [opaque pointer types] Push the passing of value types up from Function/GlobalVariable to GlobalObject
(coming next, pushing this up into GlobalValue, so it can store the
value type directly)

llvm-svn: 245742
2015-08-21 21:35:28 +00:00
Hal Finkel
8f05a818d7 [PowerPC] PPCVSXFMAMutate should not segfault on undef input registers
When PPCVSXFMAMutate would look at the input addend register, it would get its
input value number. This would fail, however, if the register was undef,
causing a segfault. Don't segfault (just skip such FMA instructions).

Fixes the test case from PR24542 (although that may have been over-reduced).

llvm-svn: 245741
2015-08-21 21:34:24 +00:00
Alex Lorenz
6fab7d4ea6 AsmParser: Save and restore the parsing state for types using SlotMapping.
This commit extends the 'SlotMapping' structure and includes mappings for named
and numbered types in it. The LLParser is extended accordingly to fill out
those mappings at the end of module parsing.

This information is useful when we want to parse standalone constant values
at a later stage using the 'parseConstantValue' method. The constant values
can be constant expressions, which can contain references to types. In order
to parse such constant values, we have to restore the internal named and
numbered mappings for the types in LLParser, otherwise the parser will report
a parsing error. Therefore, this commit also introduces a new method called
'restoreParsingState' to LLParser, which uses the slot mappings to restore
some of its internal parsing state.

This commit is required to serialize constant value pointers in the machine
memory operands for the MIR format.

Reviewers: Duncan P. N. Exon Smith
llvm-svn: 245740
2015-08-21 21:32:39 +00:00
Bruno Cardoso Lopes
0dc7d0fbc7 [LVI] Use a SmallVector instead of SmallPtrSet. NFC
llvm-svn: 245739
2015-08-21 21:18:26 +00:00
Alex Lorenz
745ed2743c MIRLangRef: Describe the syntax for the immediate operands, register values,
register operands and register flags.

llvm-svn: 245738
2015-08-21 21:17:01 +00:00
Alex Lorenz
5f32ed0eca MIR Serialization: Print MCSymbol operands.
This commit allows the MIR printer to print the MCSymbol machine operands.
Unfortunately they can't be parsed at this time. I will create a bug that will
track the fact that the MCSymbol operands can't be parsed yet.

llvm-svn: 245737
2015-08-21 21:12:44 +00:00
Simon Pilgrim
a6ae3df1c8 Line endings fix.
llvm-svn: 245736
2015-08-21 21:09:51 +00:00
Sanjay Patel
1562e12359 [x86] enable machine combiner reassociations for 256-bit vector min/max
llvm-svn: 245735
2015-08-21 21:04:21 +00:00
Sanjay Patel
256ad9fa9f remove 'FeatureSlowUAMem' from AMD CPUs based on 10H micro-arch or later
See discussion in D12154 ( http://reviews.llvm.org/D12154 ), AMD Software
Optimization Guides for 10H/12H/15H/16H, and Agner Fog's experimental data.

llvm-svn: 245733
2015-08-21 20:39:17 +00:00
Davide Italiano
256ba29add [llvm-readobj] Add support for MachO DataInCodeDataCommand.
Example output:

File: <stdin>
Format: Mach-O arm
Arch: arm
AddressSize: 32bit
DataInCode {
  Data offset: 300
  Data size: 32
  Data Regions [
    DICE {
      Index: 0
      Offset: 0
      Length: 4
      Kind: 1
    }
    DICE {
      Index: 1
      Offset: 4
      Length: 4
      Kind: 4
    }
    DICE {
      Index: 2
      Offset: 8
      Length: 2
      Kind: 3
    }
    DICE {
      Index: 3
      Offset: 10
      Length: 1
      Kind: 2
    }
  ]
}

Differential Revision:	 http://reviews.llvm.org/D12084

llvm-svn: 245732
2015-08-21 20:28:30 +00:00
David Blaikie
68bf0df954 Add comment as follow up to r245712
llvm-svn: 245730
2015-08-21 20:18:39 +00:00
Sanjay Patel
f63481a93c [x86] invert logic for attribute 'FeatureFastUAMem'
This is a 'no functional change intended' patch. It removes one FIXME, but adds several more.

Motivation: the FeatureFastUAMem attribute may be too general. It is used to determine if any
sized misaligned memory access under 32-bytes is 'fast'. From the added FIXME comments, however,
you can see that we're not consistent about this. Changing the name of the attribute makes it
clearer to see the logic holes.

Changing this to a 'slow' attribute also means we don't have to add an explicit 'fast' attribute
to new chips; fast unaligned accesses have been standard for several generations of CPUs now.

Differential Revision: http://reviews.llvm.org/D12154

llvm-svn: 245729
2015-08-21 20:17:26 +00:00
David Blaikie
98f759d4d6 [opaque pointer type]: Pass explicit pointee type when building a constant GEP.
Gets a bit tricky in the ValueMapper, of course - not sure if we should
just expose a list of explicit types for each Value so that the
ValueMapper can be neutral to these special cases (it's OK for things
like load, where the explicit type is the result type - but when that's
not the case, it means plumbing through another "special" type... )

llvm-svn: 245728
2015-08-21 20:16:51 +00:00
Peter Collingbourne
9092fbc31c llvm-lto: Re-order code.
This saves us from needing to asave a pointer, and will be needed for an
upcoming ownership change.

llvm-svn: 245722
2015-08-21 19:09:42 +00:00
Dan Liew
dd489fffd3 Filter libraries that are not installed out of CMake exports (currently
gtest and gtest_main) when generating ``Makefile.llvmbuild``.

Libraries that are not installed should not be exported because they
won't be available from an install tree.  Rather than filtering out the
gtest libraries in cmake/modules/Makefile, simply teach llvm-build to
filter out libraries that will not be installed from its generated list
of exported libraries.

Note that LLVMBUILD_LIB_DEPS_* are used during our own CMake build
process so we cannot filter LLVMBUILD_LIB_DEPS_gtest* out in llvm-build.
We must leave this gtest filter logic in cmake/modules/Makefile.

llvm-svn: 245718
2015-08-21 18:10:57 +00:00
Dan Liew
3e6b9ffdd7 llvm-build: Adopt generation of LLVM_LIBS_TO_EXPORT. Patch by
Brad King.

Move `LLVM_LIBS_TO_EXPORT` over to Makefile.llvmbuild and generate it
from `llvm-build` using the same logic used to export the dependencies
of these libraries.  This avoids depending on `llvm-config`.

This refactoring was originally motivated by issue #24154 due to commit
r243297 (Fix `llvm-config` to emit the linker flag for the combined
shared object, 2015-07-27) changing the output of `llvm-config --libs`
to not have the individual libraries when we configure with
`--enable-shared`.  That change was reverted by r244108 but this
refactoring makes sense on its own anyway.

llvm-svn: 245717
2015-08-21 18:10:55 +00:00
Dan Liew
8de69c75c0 llvm-build: Factor out duplicate cmake export listing. Patch by
Brad King.

The write_cmake_fragment and write_cmake_exports_fragment methods share
some logic for selecting libraries that CMake needs to know about.
Factor it out into a helper to avoid duplication.

llvm-svn: 245716
2015-08-21 18:10:51 +00:00
Sanjay Patel
2e11124ece [x86] enable machine combiner reassociations for 128-bit vector min/max
llvm-svn: 245715
2015-08-21 18:06:49 +00:00
David Blaikie
25f1840e3c Remove an unnecessary use of pointee types introduced in r194220
David Majnemer (the original author) believes this to be an impossible
condition to reach anyway, and no test cases cover this so we'll go with
that.

llvm-svn: 245712
2015-08-21 17:37:41 +00:00
Yaron Keren
6479d6085a Disable Visual C++ 2013 Debug mode assert on null pointer in some STL algorithms,
such as std::equal on the third argument. This reverts previous workarounds.

Predefining _DEBUG_POINTER_IMPL disables Visual C++ 2013 headers from defining
it to a function performing the null pointer check. In practice, it's not that
bad since any function actually using the nullptr will seg fault. The other
iterator sanity checks remain enabled in the headers.

Reviewed by Aaron Ballmanþ and Duncan P. N. Exon Smith.

llvm-svn: 245711
2015-08-21 17:31:03 +00:00
Alex Lorenz
8cbcac8263 MIRLangRef: Describe the syntax for machine instruction names and flags.
llvm-svn: 245710
2015-08-21 17:26:38 +00:00
Sanjay Patel
a4ce8ba2fe save some testing time; get rid of the non-SSE chips in this test
It doesn't matter what slow/fast unaligned attribute the old chips
have - they can't use anything more than 4-byte stores.

llvm-svn: 245709
2015-08-21 17:16:51 +00:00
Benjamin Kramer
66364e9437 [APFloat] Remove else after return and replace loop with std::equal. NFC.
llvm-svn: 245707
2015-08-21 16:44:52 +00:00
Eric Christopher
11122e529d Fix typo - symetric -> symmetric.
llvm-svn: 245705
2015-08-21 16:23:39 +00:00
Sanjay Patel
4bb1f6d4ba add a test case to check the fast-unaligned-mem attribute per CPU
This will confirm that the patch in D12154 is actually NFC.
It will also confirm that the proposed changes for the AMD chips
are behaving as expected.

llvm-svn: 245704
2015-08-21 16:08:26 +00:00
John Brawn
bb9783495b [DAGCombiner] Fold together mul and shl when both are by a constant
This is intended to improve code generation for GEPs, as the index value is
shifted by the element size and in GEPs of multi-dimensional arrays the index
of higher dimensions is multiplied by the lower dimension size.

Differential Revision: http://reviews.llvm.org/D12197

llvm-svn: 245689
2015-08-21 10:48:17 +00:00
NAKAMURA Takumi
9d82bd7d88 Revert r245635, "[InstCombine] Transform A & (L - 1) u< L --> L != 0"
It caused miscompilation in clang.

llvm-svn: 245678
2015-08-21 07:46:07 +00:00
Mohammad Shahid
7e7f78516e Test Commit: Reformats 2 lines in LangRef.rst
llvm-svn: 245673
2015-08-21 05:31:07 +00:00
Peter Collingbourne
482995ea0a Linker: Remove empty destructor.
llvm-svn: 245672
2015-08-21 04:51:24 +00:00
Peter Collingbourne
e7628d5684 LTO: Simplify ownership of LTOCodeGenerator::TargetMach.
llvm-svn: 245671
2015-08-21 04:45:57 +00:00
Peter Collingbourne
1a4134b22f LTO: Simplify ownership of LTOCodeGenerator::CodegenOptions.
llvm-svn: 245670
2015-08-21 04:45:55 +00:00
James Y Knight
af99ad073e [Sparc] Support user-specified stack object overalignment.
Note: I do not implement a base pointer, so it's still impossible to
have dynamic realignment AND dynamic alloca in the same function.

This also moves the code for determining the frame index reference
into getFrameIndexReference, where it belongs, instead of inline in
eliminateFrameIndex.

[Begin long-winded screed]

Now, stack realignment for Sparc is actually a silly thing to support,
because the Sparc ABI has no need for it -- unlike the situation on
x86, the stack is ALWAYS aligned to the required alignment for the CPU
instructions: 8 bytes on sparcv8, and 16 bytes on sparcv9.

However, LLVM unfortunately implements user-specified overalignment
using stack realignment support, so for now, I'm going to go along
with that tradition. GCC instead treats objects which have alignment
specification greater than the maximum CPU-required alignment for the
target as a separate block of stack memory, with their own virtual
base pointer (which gets aligned). Doing it that way avoids needing to
implement per-target support for stack realignment, except for the
targets which *actually* have an ABI-specified stack alignment which
is too small for the CPU's requirements.

Further unfortunately in LLVM, the default canRealignStack for all
targets effectively returns true, despite that implementing that is
something a target needs to do specifically. So, the previous behavior
on Sparc was to silently ignore the user's specified stack
alignment. Ugh.

Yet MORE unfortunate, if a target actually does return false from
canRealignStack, that also causes the user-specified alignment to be
*silently ignored*, rather than emitting an error.

(I started looking into fixing that last, but it broke a bunch of
tests, because LLVM actually *depends* on having it silently ignored:
some architectures (e.g. non-linux i386) have smaller stack alignment
than spilled-register alignment. But, the fact that a register needs
spilling is not known until within the register allocator. And by that
point, the decision to not reserve the frame pointer has been frozen
in place. And without a frame pointer, stack realignment is not
possible. So, canRealignStack() returns false, and
needsStackRealignment() then returns false, assuming everyone can just
go on their merry way assuming the alignment requirements were
probably just suggestions after-all. Sigh...)

Differential Revision: http://reviews.llvm.org/D12208

llvm-svn: 245668
2015-08-21 04:17:56 +00:00
Peter Collingbourne
96b0ffdce8 TransformUtils: Introduce module splitter.
The module splitter splits a module into linkable partitions. It will
be used to implement parallel LTO code generation.

This initial version of the splitter does not attempt to deal with the
somewhat subtle symbol visibility issues around module splitting. These
will be dealt with in a future change.

Differential Revision: http://reviews.llvm.org/D12132

llvm-svn: 245662
2015-08-21 02:48:20 +00:00