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Commit Graph

184704 Commits

Author SHA1 Message Date
Fangrui Song
237f8ee8eb [llvm-nm] Fix -DBUILD_SHARED_LIBS=ON builds after D66160/r371576
llvm-svn: 371585
2019-09-11 01:49:00 +00:00
Petr Hosek
1b31f282e7 clang-misexpect: Profile Guided Validation of Performance Annotations in LLVM
This patch contains the basic functionality for reporting potentially
incorrect usage of __builtin_expect() by comparing the developer's
annotation against a collected PGO profile. A more detailed proposal and
discussion appears on the CFE-dev mailing list
(http://lists.llvm.org/pipermail/cfe-dev/2019-July/062971.html) and a
prototype of the initial frontend changes appear here in D65300

We revised the work in D65300 by moving the misexpect check into the
LLVM backend, and adding support for IR and sampling based profiles, in
addition to frontend instrumentation.

We add new misexpect metadata tags to those instructions directly
influenced by the llvm.expect intrinsic (branch, switch, and select)
when lowering the intrinsics. The misexpect metadata contains
information about the expected target of the intrinsic so that we can
check against the correct PGO counter when emitting diagnostics, and the
compiler's values for the LikelyBranchWeight and UnlikelyBranchWeight.
We use these branch weight values to determine when to emit the
diagnostic to the user.

A future patch should address the comment at the top of
LowerExpectIntrisic.cpp to hoist the LikelyBranchWeight and
UnlikelyBranchWeight values into a shared space that can be accessed
outside of the LowerExpectIntrinsic pass. Once that is done, the
misexpect metadata can be updated to be smaller.

In the long term, it is possible to reconstruct portions of the
misexpect metadata from the existing profile data. However, we have
avoided this to keep the code simple, and because some kind of metadata
tag will be required to identify which branch/switch/select instructions
are influenced by the use of llvm.expect

Patch By: paulkirth
Differential Revision: https://reviews.llvm.org/D66324

llvm-svn: 371584
2019-09-11 01:09:16 +00:00
David Blaikie
782e774b4d Revert "llvm-reduce: Add pass to reduce parameters"
Looks to be failing on asan buildbots

This reverts commit r371567.

llvm-svn: 371580
2019-09-11 00:44:17 +00:00
Petr Hosek
ada598f6b5 Revert "Adding support for overriding LLVM_ENABLE_RUNTIMES for runtimes builds."
This reverts commit r371566: this doesn't correctly handle the case
where LLVM_ENABLE_RUNTIMES contains a list of values.

llvm-svn: 371579
2019-09-11 00:43:35 +00:00
Cyndy Ishida
2fa52a1992 [Object][TextAPI] NFC, fix tapi lit tests
FileCheck command had wrong casing, which works fine on macOS, repairs the linux build bots

llvm-svn: 371577
2019-09-11 00:13:01 +00:00
Cyndy Ishida
5c9f000ded [llvm-nm] Add tapi file support
Summary:
This commit is the final one for adding tapi support to the llvm-nm implementation.
This commit also has accompanying tests the additions to lib/Object

Reviewers: ributzka, steven_wu

Reviewed By: ributzka

Subscribers: hiraditya, plotfi, dexonsmith, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66160

llvm-svn: 371576
2019-09-11 00:00:53 +00:00
Alina Sbirlea
214fc9a6b8 [MemorySSA] MemorySSA should not model debuginfo, and need not update it.
Reverts the change in r371084, but keeps the test.
After r371565, debuginfo cannot be modelled in MemorySSA, even with a
non-standard AA pipeline.

llvm-svn: 371573
2019-09-10 23:36:43 +00:00
Jessica Paquette
d43577fdd6 [GlobalISel] When a tail call is emitted in a block, stop translating it
This fixes a crash in tail call translation caused by assume and lifetime_end
intrinsics.

It's possible to have instructions other than a return after a tail call which
will still have `Analysis::isInTailCallPosition` return true. (Namely,
lifetime_end and assume intrinsics.)

If we emit a tail call, we should stop translating instructions in the block.
Otherwise, we can end up emitting an extra return, or dead instructions in
general. This makes the verifier unhappy, and is generally unfortunate for
codegen.

This also removes the code from AArch64CallLowering that checks if we have a
tail call when lowering a return. This is covered by the new code now.

Also update call-translator-tail-call.ll to show that we now properly tail call
in the presence of lifetime_end and assume.

Differential Revision: https://reviews.llvm.org/D67415

llvm-svn: 371572
2019-09-10 23:34:45 +00:00
Jessica Paquette
da7fa59d26 [AArch64][GlobalISel] Support sibling calls with mismatched calling conventions
Add support for sibcalling calls whose calling convention differs from the
caller's.

- Port over `CCState::resultsCombatible` from CallingConvLower.cpp into
  CallLowering. This is used to verify that the way the caller and callee CC
  handle incoming arguments matches up.

- Add `CallLowering::analyzeCallResult`. This is basically a port of
  `CCState::AnalyzeCallResult`, but using `ArgInfo` rather than `ISD::InputArg`.

- Add `AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay`. This checks
  that the calling conventions are compatible, and that the caller and callee
  preserve the same registers.

For testing:

- Update call-translator-tail-call.ll to show that we can now handle this.

- Add a GISel line to tailcall-ccmismatch.ll to show that we will not tail call
  when the regmasks don't line up.

Differential Revision: https://reviews.llvm.org/D67361

llvm-svn: 371570
2019-09-10 23:25:12 +00:00
Alina Sbirlea
50d7aa39ab Update ReleaseNotes: add enabling of MemorySSA.
llvm-svn: 371569
2019-09-10 23:22:37 +00:00
Amy Huang
062b5d40cb Reland "Change the X86 datalayout to add three address spaces
for 32 bit signed, 32 bit unsigned, and 64 bit pointers."
This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5.

Original review at https://reviews.llvm.org/D64931.
Review for added fix at https://reviews.llvm.org/D66843.

llvm-svn: 371568
2019-09-10 23:15:38 +00:00
David Blaikie
5d92ad29cd llvm-reduce: Add pass to reduce parameters
Patch by Diego Treviño!

Differential Revision: https://reviews.llvm.org/D65479

llvm-svn: 371567
2019-09-10 23:10:10 +00:00
Puyan Lotfi
eff852c2ce Adding support for overriding LLVM_ENABLE_RUNTIMES for runtimes builds.
On some platforms, certain runtimes are not supported. For runtimes builds of
those platforms it would be nice if we could disable certain runtimes (ie
libunwind on Windows).



Differential Revision: https://reviews.llvm.org/D67195

llvm-svn: 371566
2019-09-10 22:55:47 +00:00
Alina Sbirlea
6c7410c453 [MemorySSA] Do not create memoryaccesses for debug info intrinsics.
Summary:
Do not model debuginfo intrinsics in MemorySSA.
Regularly these are non-memory modifying instructions. With -disable-basicaa, they were being modelled as Defs.

Reviewers: george.burgess.iv

Subscribers: aprantl, Prazek, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67307

llvm-svn: 371565
2019-09-10 22:35:27 +00:00
David Blaikie
1838a8484f llvm-reduce: Remove some unused headers/more narrowly include them
llvm-svn: 371564
2019-09-10 22:31:35 +00:00
David Blaikie
ae5ca81983 llvm-remove: Remove "using namespace" in header.
llvm-svn: 371563
2019-09-10 22:10:00 +00:00
David Blaikie
4e25fb2d4f llvm-reduce: Add pass to reduce Metadata
Patch by Diego Treviño!

Differential Revision: https://reviews.llvm.org/D65026

llvm-svn: 371562
2019-09-10 22:09:58 +00:00
Eric Christopher
24de559445 Move LLVM_ENABLE_ABI_BREAKING_CHECKS variables to their own file
so that you don't have to link Error.o and all of its dependencies.

In more detail: global initializers in Error.o can't be elided with
-ffunction-sections/-gc-sections since they always need to be run
causing a fairly significant binary bloat if all you want is the
ABI breaking checks code.

Differential Revision: https://reviews.llvm.org/D67387

llvm-svn: 371561
2019-09-10 22:05:01 +00:00
Philip Reames
9c14f5f07c [Loads] Move generic code out of vectorizer into a location it might be reused [NFC]
llvm-svn: 371558
2019-09-10 21:33:53 +00:00
Philip Reames
5e61658cdf [ValueTracking] Factor our common speculation suppression logic [NFC]
Expose a utility function so that all places which want to suppress speculation (when otherwise legal) due to ordering and/or sanitizer interaction can do so.

llvm-svn: 371556
2019-09-10 21:12:29 +00:00
David Blaikie
6de21dfa20 llvm-reduce: Simplify testing using -implicit-check-not
Also fix llvm-reduce to use the specified output file name directly,
without appending '.ll' to the name.

llvm-svn: 371555
2019-09-10 20:52:14 +00:00
Sanjay Patel
b5245bbc48 [x86] add test for false dependency with AVX; NFC
Goes with D67363

llvm-svn: 371551
2019-09-10 20:04:10 +00:00
Roman Lebedev
740ba98eb1 [NFC][InstCombine] rewrite test added in r371537 to use non-null pointer instead
I only want to ensure that %offset is non-zero there,
it doesn't matter how that info is conveyed.
As filed in PR43267, the assumption way does not work.

llvm-svn: 371550
2019-09-10 19:30:17 +00:00
Philip Reames
4760eefc51 [X86] Updated target specific selection dag code to conservatively check for isAtomic in addition to isVolatile
See D66309 for context.

This is the first sweep of x86 target specific code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time.

Sorry for the lack of tests.  As discussed in the review, most of these are vector tests (for which atomicity is not well defined) and I couldn't figure out to exercise the anyextend cases which aren't vector specific.

Differential Revision: https://reviews.llvm.org/D66322

llvm-svn: 371547
2019-09-10 18:43:15 +00:00
Roman Lebedev
5fafff6179 [NFC][InstSimplify] rewrite test added in r371537 to use non-null pointer instead
I only want to ensure that %offset is non-zero there,
it doesn't matter how that info is conveyed.
As filed in PR43267, the assumption way does not work.

llvm-svn: 371546
2019-09-10 18:40:00 +00:00
Matt Arsenault
2c4cefbd49 GlobalISel/TableGen: Handle REG_SEQUENCE patterns
The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit
operation.

llvm-svn: 371542
2019-09-10 17:57:33 +00:00
Guozhi Wei
0dffa591e6 [BPI] Adjust the probability for floating point unordered comparison
Since NaN is very rare in normal programs, so the probability for floating point unordered comparison should be extremely small. Current probability is 3/8, it is too large, this patch changes it to a tiny number.

Differential Revision: https://reviews.llvm.org/D65303

llvm-svn: 371541
2019-09-10 17:25:11 +00:00
Matt Arsenault
4761b0557b AMDGPU/GlobalISel: Select G_FABS/G_FNEG
f64 doesn't work yet because tablegen currently doesn't handlde
REG_SEQUENCE.

This does regress some multi use VALU fneg cases since now the
immediate remains in an SGPR, and more moves are used for legalizing
the xor. This is a SIFixSGPRCopies deficiency.

llvm-svn: 371540
2019-09-10 17:19:46 +00:00
Matt Arsenault
db4c600d39 AMDGPU/GlobalISel: Select cvt pk intrinsics
llvm-svn: 371539
2019-09-10 17:17:05 +00:00
Matt Arsenault
3101dd42af AMDGPU/GlobalISel: Select llvm.amdgcn.sffbh
llvm-svn: 371538
2019-09-10 17:16:59 +00:00
Roman Lebedev
fa332982e3 [NFC][InstCombine][InstSimplify] PR43251 - and some patterns with offset != 0
https://rise4fun.com/Alive/21b

llvm-svn: 371537
2019-09-10 17:13:59 +00:00
Matt Arsenault
3ded3d2e85 AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
llvm-svn: 371536
2019-09-10 16:42:37 +00:00
Matt Arsenault
8caf5c30ab AMDGPU/GlobalISel: Legalize constant 32-bit loads
Legalize by casting to a 64-bit constant address. This isn't how the
DAG implements it, but it should.

llvm-svn: 371535
2019-09-10 16:42:31 +00:00
Sam Elliott
b390d5a473 [RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.

This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.

This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.

Reviewers: luismarques, asb

Reviewed By: luismarques, asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66139

llvm-svn: 371534
2019-09-10 16:24:03 +00:00
Matt Arsenault
c9c0200f87 AMDGPU/GlobalISel: First pass at attempting to legalize load/stores
There's still a lot more to do, but this handles decomposing due to
alignment. I've gotten it to the point where nothing crashes or
infinite loops the legalizer.

llvm-svn: 371533
2019-09-10 16:20:14 +00:00
Sam Elliott
583fbc8d08 [RISCV] Add Option for Printing Architectural Register Names
Summary:
This is an option primarily to use during testing. Instead of always
printing registers using their ABI names, this allows a user to request they
are printed with their architectural name.

This is then used in the register constraint tests to ensure the mapping
between architectural and abi names is correct.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65950

llvm-svn: 371531
2019-09-10 15:55:55 +00:00
Sanjay Patel
f70224dfd4 [x86] add a test for BreakFalseDeps; NFC
As discussed in D67363

llvm-svn: 371528
2019-09-10 15:42:22 +00:00
Djordje Todorovic
0dec37607c Revert "[utils] Implement the llvm-locstats tool"
This reverts commit rL371520.

llvm-svn: 371527
2019-09-10 14:48:52 +00:00
Sanjay Patel
03eee64f7d [ARM] add test for BreakFalseDeps with minsize attribute; NFC
llvm-svn: 371526
2019-09-10 14:29:02 +00:00
Simon Pilgrim
81e64ab378 [X86] Add AVX partial dependency tests as noted on D67363
llvm-svn: 371525
2019-09-10 14:28:29 +00:00
Sanjay Patel
923f5e09a6 [ARM] auto-generate complete test checks; NFC
llvm-svn: 371524
2019-09-10 14:26:25 +00:00
Florian Hahn
0d4d8faf97 [VectorUtils] Remove unused include. [NFC]
Patch by Francesco Petrogalli <francesco.petrogalli@arm.com>

Reviewers: fhahn

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D67365

llvm-svn: 371523
2019-09-10 14:20:20 +00:00
David Zarzycki
99a2867820 [CMake] Don't pass all LLVM_COMPILE_FLAGS to the C compiler
GCC (unlike clang!) warns about C++ flags when compiling C.

https://reviews.llvm.org/D67171

llvm-svn: 371521
2019-09-10 14:19:52 +00:00
Djordje Todorovic
64810143df [utils] Implement the llvm-locstats tool
The tool reports verbose output for the DWARF debug location coverage.
The llvm-locstats for each variable or formal parameter DIE computes what
percentage from the code section bytes, where it is in scope, it has
location description. The line 0 shows the number (and the percentage) of
DIEs with no location information, but the line 100 shows the number (and
the percentage) of DIEs where there is location information in all code
section bytes (where the variable or parameter is in the scope). The line
50..59 shows the number (and the percentage) of DIEs where the location
information is in between 50 and 59 percentage of its scope covered.

The tool will be very useful for tracking improvements regarding the
"debugging optimized code" support with LLVM ecosystem.

Differential Revision: https://reviews.llvm.org/D66526

llvm-svn: 371520
2019-09-10 13:47:03 +00:00
Roman Lebedev
c766525476 [NFC][InstCombine] PR43251 - valid for other predicates too
llvm-svn: 371519
2019-09-10 13:29:40 +00:00
Florian Hahn
830d01fc77 [InstCombine] Use SimplifyFMulInst to simplify multiply in fma.
This allows us to fold fma's that multiply with 0.0. Also, the
multiply by 1.0 case is handled there as well. The fneg/fabs cases
are not handled by SimplifyFMulInst, so we need to keep them.

Reviewers: spatel, anemet, lebedev.ri

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D67351

llvm-svn: 371518
2019-09-10 13:10:28 +00:00
Florian Hahn
558647cd11 [InstCombine] Precommit tests for D67351.
llvm-svn: 371517
2019-09-10 13:05:34 +00:00
Sanjay Patel
352df711d7 [BreakFalseDeps] fix typos/grammar in documentation comment; NFC
llvm-svn: 371516
2019-09-10 13:00:31 +00:00
Martin Storsjo
02e4bfbc70 [Object] Implement relocation resolver for COFF ARM/ARM64
Adding testscases for this via llvm-dwarfdump.

Also add testcases for the existing resolver support for X86.

Differential Revision: https://reviews.llvm.org/D67340

llvm-svn: 371515
2019-09-10 12:31:40 +00:00
Haojian Wu
fa6d5378ba Fix the "git modified" issue on the preserve-comments-crlf.s.
Summary:
 rL371473 corrected the line ending (to crlf) in preserve-comments-crlf.s, but it causes a wired issue on git
 repository (I ran git pull today, it showed a local change of that file even I did not change anything).

Reviewers: gribozavr

Reviewed By: gribozavr

Subscribers: llvm-commits, cfe-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67391

llvm-svn: 371513
2019-09-10 12:17:49 +00:00