Dan Gohman
89660301e3
Rename ConstantSDNode::getValue to getZExtValue, for consistency
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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Dan Gohman
ebba07cccf
Tablegen generated code already tests the opcode value, so it's not
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necessary to use dyn_cast in these predicates.
llvm-svn: 55055
2008-08-20 15:24:22 +00:00
Dan Gohman
9742f7772d
Rename SDOperand to SDValue.
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llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Mon P Wang
7d89d61387
Added MemOperands to Atomic operations since Atomics touches memory.
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Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub
llvm-svn: 52706
2008-06-25 08:15:39 +00:00
Evan Cheng
11d2c09adc
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Bill Wendling
2cae66e28b
Final de-tabification.
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llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Andrew Lenharth
db9cd46f5d
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet
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llvm-svn: 47430
2008-02-21 06:45:13 +00:00
Andrew Lenharth
c178981b85
llvm.memory.barrier, and impl for x86 and alpha
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llvm-svn: 47204
2008-02-16 01:24:58 +00:00
Chris Lattner
6846e346a8
rename SDTRet -> SDTNone.
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Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner
9b4f2b2316
get def use info more correct.
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llvm-svn: 45821
2008-01-10 05:12:37 +00:00
Chris Lattner
14310afe42
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
8b4b75c771
Change the 'isStore' inferrer to look for 'SDNPMayStore'
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instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
llvm-svn: 45654
2008-01-06 06:44:58 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
64a1febf9a
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
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llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Andrew Lenharth
6e449dc482
something wrong with this opt
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llvm-svn: 44370
2007-11-27 18:31:30 +00:00
Bill Wendling
934fcd87e7
Unifacalize the CALLSEQ{START,END} stuff.
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llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
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adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce
Add a flag for indirect branch instructions.
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Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
Evan Cheng
b43255bc68
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng
53cb03b583
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Andrew Lenharth
c894d4e3ce
Use this nifty Constraints thing and fix the inverted conditional moves
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llvm-svn: 36191
2007-04-17 04:07:59 +00:00
Andrew Lenharth
42ced99f24
FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available
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llvm-svn: 33492
2007-01-24 21:09:16 +00:00
Andrew Lenharth
8261b94b09
Be sure to grab weak functions too, and make implicit defs comments
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llvm-svn: 32308
2006-12-07 17:39:14 +00:00
Chris Lattner
13ae6835d9
silence warnings.
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llvm-svn: 31394
2006-11-03 01:18:29 +00:00
Andrew Lenharth
c43c2d6966
fix 2006-11-01-vastart.ll
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llvm-svn: 31371
2006-11-02 03:05:26 +00:00
Andrew Lenharth
92b6c807c7
more shotenning
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llvm-svn: 31331
2006-10-31 23:46:56 +00:00
Andrew Lenharth
cc672e3b2b
Let us play simplify the td file (and fix a few missed sub and mul patterns).
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llvm-svn: 31322
2006-10-31 19:52:12 +00:00
Andrew Lenharth
c4f8836525
Add all that branch mangling niftiness
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llvm-svn: 31313
2006-10-31 16:49:55 +00:00
Evan Cheng
fe5bb5dbe6
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
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llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Chris Lattner
80790cad34
adjcallstack up/down clobbers the sp
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llvm-svn: 30910
2006-10-12 18:00:14 +00:00
Chris Lattner
b9c1ea6dcc
Use cute tblgen tricks to make zap handling more powerful. Specifically,
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when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.
This compiles Alpha/zapnot4.ll into:
sll $16,3,$0
zapnot $0,3,$0
ret $31,($26),1
instead of:
ldah $0,1($31)
lda $0,-8($0)
sll $16,3,$1
and $1,$0,$0
ret $31,($26),1
It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha. Make andrew will do this.
llvm-svn: 30875
2006-10-11 05:13:56 +00:00
Chris Lattner
95a8905db2
Remove dead/redundant instructions. These are handled by ZAPNOTi
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llvm-svn: 30872
2006-10-11 04:12:39 +00:00
Evan Cheng
d22f3dd3ed
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
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llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Andrew Lenharth
d12f2d614a
catch constants more often
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llvm-svn: 30534
2006-09-20 15:05:49 +00:00
Andrew Lenharth
5d958d3405
Jump tables on Alpha
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llvm-svn: 30463
2006-09-18 18:01:03 +00:00
Evan Cheng
34a49551f5
CALLSEQ_* produces chain even if that's not needed.
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llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Evan Cheng
7e30f4efe7
Remove a duplicate pattern/
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llvm-svn: 29413
2006-07-31 18:42:49 +00:00
Andrew Lenharth
fe127f3de7
Let the alpha breakage begin. First Formals and RET. next Calls
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llvm-svn: 28753
2006-06-12 18:09:24 +00:00
Andrew Lenharth
813c3dcf58
ignore ordered/unordered for now
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llvm-svn: 28679
2006-06-04 00:25:51 +00:00
Andrew Lenharth
4760eaae91
support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4
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llvm-svn: 27370
2006-04-03 04:19:17 +00:00
Andrew Lenharth
af4a638eab
mul by const conversion sequences. more coming soon
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llvm-svn: 27368
2006-04-03 03:18:59 +00:00
Andrew Lenharth
f124519fc8
fcopysign for mixed mode
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llvm-svn: 26651
2006-03-09 17:56:33 +00:00
Andrew Lenharth
e08d165146
alpha and llvm have different oppinions on which arg is the sign bit
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llvm-svn: 26647
2006-03-09 17:41:50 +00:00
Andrew Lenharth
25de2846c5
Alpha Scheduling classes
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llvm-svn: 26643
2006-03-09 17:16:45 +00:00
Andrew Lenharth
c180d749a2
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
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llvm-svn: 26641
2006-03-09 14:58:25 +00:00
Andrew Lenharth
c879542ab0
isStoreToStackSlot
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llvm-svn: 25925
2006-02-03 03:07:37 +00:00
Andrew Lenharth
9812806d03
Add immediate forms of cmov and remove some cruft
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llvm-svn: 25882
2006-02-01 19:37:33 +00:00
Chris Lattner
7a06abe72b
cmovle != cmovlt
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llvm-svn: 25761
2006-01-29 03:47:30 +00:00
Chris Lattner
20d4194a0d
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00