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Commit Graph

207104 Commits

Author SHA1 Message Date
Sanjay Patel
1cf013898b [SLP] avoid unreachable code crash/infloop
Example based on the post-commit comments for D88735.
2020-11-17 15:10:23 -05:00
Jon Roelofs
8e1729917d [MachineScheduler] Inform pass infra of post-ra scheduler's dependencies
Differential Revision: https://reviews.llvm.org/D91561
2020-11-17 10:56:12 -08:00
Sanjay Patel
8beb4e5570 [InstCombine] allow vectors for masked-add -> xor fold
https://rise4fun.com/Alive/I4Ge

  Name: add with pow2 mask
  Pre: isPowerOf2(C2) && (C1 & C2) != 0 && (C1 & (C2-1)) == 0
  %a = add i8 %x, C1
  %r = and i8 %a, C2
  =>
  %n = and i8 %x, C2
  %r = xor i8 %n, C2
2020-11-17 13:36:08 -05:00
Simon Pilgrim
5ab8e1f9ab [X86] byval tests - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 18:32:44 +00:00
Simon Pilgrim
2de775338d [X86] emutls.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 18:32:43 +00:00
Simon Pilgrim
8e56727854 [X86] emutls-pie.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 18:32:43 +00:00
Simon Pilgrim
fcb60d0ff7 [X86] emutls-pic.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 18:32:42 +00:00
Simon Pilgrim
f7c410add4 [X86] segmented-stacks tests - replace X32 check prefix with X86 for non-gnux32 tests. NFC.
Only use X32 for the gnux32 triples in the tests
2020-11-17 17:59:22 +00:00
Simon Pilgrim
bb6b31f9fc [X86] select-of-fp-constants.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 17:59:22 +00:00
Simon Pilgrim
c7c2312a5d [InstCombine] visitAnd - remove unnecessary Value *X, *Y shadow variables. NFCI.
Fixes a number of Wshadow warnings.
2020-11-17 17:59:21 +00:00
Simon Pilgrim
4140b396a9 [InstCombine] visitAnd - use m_SpecificInt instead of m_APInt + comparison. NFCI.
m_SpecificInt has the same 'no undef element' behaviour as m_APInt so no change there, and anyway we have test coverage for undef elements in the fold.

Noticed while fixing a Wshadow warning about shadow Value *X, *Y variables.
2020-11-17 17:37:10 +00:00
Simon Pilgrim
deb5c1f9b1 [X86] rot16.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 17:37:09 +00:00
Simon Pilgrim
3bfc2c9c6d [X86] vec_fabs.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 17:37:09 +00:00
Wei Wang
07da148882 [BPI] Look through bitcasts in calcZeroHeuristic
Constant hoisting may hide the constant value behind bitcast for And's
operand. Track down the constant to make the BFI result consistent
regardless of hoisting.

Differential Revision: https://reviews.llvm.org/D91450
2020-11-17 09:33:05 -08:00
Sanjay Patel
a3056e323d [InstCombine] remove scalar constraint for mask-of-add fold
https://rise4fun.com/Alive/V6fP

  Name: add with low mask
  Pre: (C1 & (-1 u>> countLeadingZeros(C2))) == 0
  %a = add i8 %x, C1
  %r = and i8 %a, C2
  =>
  %r = and i8 %x, C2
2020-11-17 12:13:45 -05:00
Sanjay Patel
7b0f05deeb [InstCombine] add vector test for mask of add; NFC 2020-11-17 12:13:45 -05:00
Sanjay Patel
12dbc7d290 [InstCombine] relax constraints on mask-of-add
There are 2 changes:
1. Remove the unnecessary one-use check.
2. Remove the unnecessary power-of-2 check.

https://rise4fun.com/Alive/V6fP

  Name: add with low mask
  Pre: (C1 & (-1 u>> countLeadingZeros(C2))) == 0
  %a = add i8 %x, C1
  %r = and i8 %a, C2
  =>
  %r = and i8 %x, C2
2020-11-17 12:13:44 -05:00
Sanjay Patel
fa666a9048 [InstCombine] add tests for masked add; NFC 2020-11-17 12:13:44 -05:00
Fangrui Song
ae0eb2cf5e [ARC] Correct ARCInstPrinter::getMnemonic after D90039 2020-11-17 09:08:36 -08:00
Nikita Popov
0fa89d71cb [BasicAA] Make alias GEP positive offset handling symmetric
aliasGEP() currently implements some special handling for the case
where all variable offsets are positive, in which case the constant
offset can be taken as the minimal offset. However, it does not
perform the same handling for the all-negative case. This means that
the alias-analysis result between two GEPs is asymmetric:
If GEP1 - GEP2 is all-positive, then GEP2 - GEP1 is all-negative,
and the first will result in NoAlias, while the second will result
in MayAlias.

Apart from producing sub-optimal results for one order, this also
violates our caching assumption. In particular, if BatchAA is used,
the cached result depends on the order of the GEPs in the first query.
This results in an inconsistency in BatchAA and AA results, which
is how I noticed this issue in the first place.

Differential Revision: https://reviews.llvm.org/D91383
2020-11-17 18:05:34 +01:00
Simon Pilgrim
cbe39bddab [PPC] Fix dead store value clang static analyzer warning. NFCI.
Simplify the SplatBits 2-byte -> 4-byte 'splat'.
2020-11-17 16:27:45 +00:00
Florian Hahn
4864887dc5 [VPlan] Add VPDef class.
This patch introduces a new VPDef class, which can be used to
manage VPValues defined by recipes/VPInstructions.

The idea here is to mirror VPUser for values defined by a recipe. A
VPDef can produce either zero (e.g. a store recipe), one (most recipes)
or multiple (VPInterleaveRecipe) result VPValues.

To traverse the def-use chain from a VPDef to its users, one has to
traverse the users of all values defined by a VPDef.

VPValues now contain a pointer to their corresponding VPDef, if one
exists. To traverse the def-use chain upwards from a VPValue, we first
need to check if the VPValue is defined by a VPDef. If it does not have
a VPDef, this means we have a VPValue that is not directly defined
iniside the plan and we are done.

If we have a VPDef, it is defined inside the region by a recipe, which
is a VPUser, and the upwards def-use chain traversal continues by
traversing all its operands.

Note that we need to add an additional field to to VPVAlue to link them
to their defs. The space increase is going to be offset by being able to
remove the SubclassID field in future patches.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D90558
2020-11-17 16:18:11 +00:00
Simon Pilgrim
62500c8769 [IR] ShuffleVectorInst::isIdentityWithPadding - bail on non-fixed-type vector shuffles.
Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=27416
2020-11-17 16:16:51 +00:00
Simon Pilgrim
1bd5b6795d [X86] nontemporal.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 16:16:51 +00:00
Simon Pilgrim
a9c95df8da [X86] subvector-broadcast.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 16:16:50 +00:00
Andy Wingo
adcc39d15d [WebAssembly] Fix parsing of linking section for named global imports
Differential Revision: https://reviews.llvm.org/D91635
2020-11-17 08:14:29 -08:00
Matt Arsenault
80d9c38cea Linker: Fix linking of byref types
This wasn't properly remapping the type like with the other
attributes, so this would end up hitting a verifier error after
linking different modules using byref.
2020-11-17 11:02:04 -05:00
Jay Foad
7e2b42617c [AMDGPU] Precommit more vccz workaround tests 2020-11-17 15:55:40 +00:00
Anton Afanasyev
fbb47aa8a7 [SLPVectorizer] Fix assert 2020-11-17 18:46:31 +03:00
Anton Afanasyev
e71c3845ad [SLP] Make SLPVectorizer to use llvm.masked.gather intrinsic
For the scattered operands of load instructions it makes sense
to use gathering load intrinsic, which can lower to native instruction
for X86/AVX512 and ARM/SVE. This also enables building
vectorization tree with entries containing scattered operands.
The next step is to add scattered store.

Fixes PR47629 and PR47623

Differential Revision: https://reviews.llvm.org/D90445
2020-11-17 18:11:45 +03:00
Andy Wingo
56125f1c87 [WebAssembly][MC] Remove useless overrides in MCWasmStreamer
Differential Revision: https://reviews.llvm.org/D91604
2020-11-17 07:09:49 -08:00
Paul C. Anagnostopoulos
d6ee0533d1 [TableGen] Clean up Target .td include files
Differential Revision: https://reviews.llvm.org/D91483
2020-11-17 09:45:14 -05:00
Florian Hahn
67e4a934d0 [ConstraintElimination] Add support for And.
When processing conditional branches, if the condition is an AND of 2 compares
and the true successor only has the current block as predecessor, queue both
conditions for the true successor.
2020-11-17 14:12:15 +00:00
Sander de Smalen
cc25d12aaf Reland [LoopVectorizer] NFCI: Calculate register usage based on TLI.getTypeLegalizationCost.
This relands https://reviews.llvm.org/D91059 and reverts commit
30fded75b48bcbc034120154a57a00c7f3d07e06.

GetRegUsage now returns 0 when Ty is not a valid vector element type.
2020-11-17 13:45:10 +00:00
Kazushi (Jam) Marukawa
09a8dd3281 [VE] Implement JumpTable
Implement JumpTable to make BRIND work on VE.  Update an existing
br_jt regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91582
2020-11-17 22:43:10 +09:00
Kazushi (Jam) Marukawa
fbe55e8d24 [VE] Correct getMnemonic
https://reviews.llvm.org/D90039 breaks VE backend.  So, fix it.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91619
2020-11-17 22:33:29 +09:00
Simon Pilgrim
5903204878 [X86] vector-sext.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 12:39:47 +00:00
Simon Pilgrim
2eb949e4b3 [X86] insert-into-constant-vector.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 12:39:47 +00:00
Simon Pilgrim
1c0c86dbe9 [X86] avx-intel-ocl.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 12:39:46 +00:00
Simon Pilgrim
df9de10e46 [X86] 2011-10-19-widen_vselect.ll - replace X32 check prefix with X86. NFC.
We typically use X32 for gnux32 triples
2020-11-17 12:39:46 +00:00
Luke Drummond
95dd3dbc4f Escape command line arguments in backtraces
A common routine is to have the compiler crash, and attempt to rerun the
cc1 command-line by copying and pasting the arguments printed by
`llvm::Support::PrettyStackProgram::print`. However, these arguments are
not quoted or escaped which means they must be manually edited before
working correctly. This patch ensures that shell-unfriendly characters
are C-escaped, and arguments with spaces are double-quoted reducing the
frustration of running cc1 inside a debugger.

As the quoting is C, this is "best effort for most shells", but should
be fine for at least bash, zsh, csh, and cmd.exe.

Reviewed by: jhenderson

Differential Revision: https://reviews.llvm.org/D90759
2020-11-17 12:16:13 +00:00
Florian Hahn
1bd32a39f9 [AsmPrinter] Use getMnemonic for instruction-mix remark.
This patch uses the new `getMnemonic` helper from D90039
to display mnemonics instead of the internal opcodes.

The main motivation behind using the mnemonics is that they
are more user-friendly and more directly related to the assembly
the users will be presented.

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D90040
2020-11-17 12:12:47 +00:00
Serge Guelton
a2767c1ec6 [build] Fix dependencies of LLVMExegesis 2020-11-17 06:15:02 -05:00
Kazushi (Jam) Marukawa
1e46f69830 [VE] Add vbrd intrinsic instructions
Add vbrd intrinsic instructions and a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91569
2020-11-17 19:04:18 +09:00
Ben Shi
2a099fbc14 [AVR] Optimize the 16-bit NEGW pseudo instruction
Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D88658
2020-11-17 17:51:58 +08:00
Florian Hahn
db0b0dabe6 [AsmWriter] Factor out mnemonic generation to accessible getMnemonic.
This patch factors out the part of printInstruction that gets the
mnemonic string for a given MCInst. This is intended to be used
subsequently for the instruction-mix remarks to display the final
mnemonic (D90040).

Unfortunately making `getMnemonic` available to the AsmPrinter
seems to require making it virtual. Not sure if there's a way around
that with the current layering of the AsmPrinters.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D90039
2020-11-17 09:47:38 +00:00
serge-sans-paille
d3fa59a7b6 [build] normalize components dependencies
Use LINK_COMPONENTS instead of explicit target_link_libraries for components.
This avoids redundancy and potential inconsistencies.

Differential Revision: https://reviews.llvm.org/D91461
2020-11-17 10:42:34 +01:00
Kai Luo
76f25ae217 [PowerPC] Add negated abs test using llvm.abs intrinsic. NFC. 2020-11-17 09:28:56 +00:00
Yevgeny Rouban
66fe9e2d79 [JumpThreading] Fix branch probabilities in DuplicateCondBranchOnPHIIntoPred()
When instructions are cloned from block BB to PredBB in the method
DuplicateCondBranchOnPHIIntoPred() number of successors of PredBB
changes from 1 to number of successors of BB. So we have to copy
branch probabilities from BB to PredBB.

Reviewed By: Kazu Hirata

Differential Revision: https://reviews.llvm.org/D90841
2020-11-17 14:40:50 +07:00
Max Kazantsev
346ccf1b4e [Test] Add one more elaborate test with LCSSA users 2020-11-17 14:37:42 +07:00