1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 22:42:46 +02:00
Commit Graph

122438 Commits

Author SHA1 Message Date
James Molloy
2543f55862 [ARM] Mark Swift MISched model as incomplete
The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.

Patch by Christof Douma!

llvm-svn: 250033
2015-10-12 12:49:59 +00:00
James Molloy
629826974b [LoopVectorize] Shrink integer operations into the smallest type possible
C semantics force sub-int-sized values (e.g. i8, i16) to be promoted to int
type (e.g. i32) whenever arithmetic is performed on them.

For targets with native i8 or i16 operations, usually InstCombine can shrink
the arithmetic type down again. However InstCombine refuses to create illegal
types, so for targets without i8 or i16 registers, the lengthening and
shrinking remains.

Most SIMD ISAs (e.g. NEON) however support vectors of i8 or i16 even when
their scalar equivalents do not, so during vectorization it is important to
remove these lengthens and truncates when deciding the profitability of
vectorization.

The algorithm this uses starts at truncs and icmps, trawling their use-def
chains until they terminate or instructions outside the loop are found (or
unsafe instructions like inttoptr casts are found). If the use-def chains
starting from different root instructions (truncs/icmps) meet, they are
unioned. The demanded bits of each node in the graph are ORed together to form
an overall mask of the demanded bits in the entire graph. The minimum bitwidth
that graph can be truncated to is the bitwidth minus the number of leading
zeroes in the overall mask.

The intention is that this algorithm should "first do no harm", so it will
never insert extra cast instructions. This is why the use-def graphs are
unioned, so that subgraphs with different minimum bitwidths do not need casts
inserted between them.

This algorithm works hard to reduce compile time impact. DemandedBits are only
queried if there are extends of illegal types and if a truncate to an illegal
type is seen. In the general case, this results in a simple linear scan of the
instructions in the loop.

No non-noise compile time impact was seen on a clang bootstrap build.

llvm-svn: 250032
2015-10-12 12:34:45 +00:00
Amjad Aboud
7b91f508e9 [X86] Add XSAVE intrinsic family
Add intrinsics for the
  XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64)
  XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64)
  XSAVEC instructions (XSAVEC/XSAVEC64)
  XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64)

Differential Revision: http://reviews.llvm.org/D13012

llvm-svn: 250029
2015-10-12 11:47:46 +00:00
Andrea Di Biagio
64ad58bc9d [x86] PR24562: fix incorrect folding of PSHUFB nodes with a mask where all indices have the most significant bit set.
This patch fixes a problem in function 'combineX86ShuffleChain' that causes a
chain of shuffles to be wrongly folded away when the combined shuffle mask has
only one element.

We may end up with a combined shuffle mask of one element as a result of
multiple calls to function 'canWidenShuffleElements()'.
Function canWidenShuffleElements attempts to simplify a shuffle mask by widening
the size of the elements being shuffled.
For every pair of shuffle indices, function canWidenShuffleElements checks if
indices refer to adjacent elements. If all pairs refer to "adjacent" elements
then the shuffle mask is safely widened. As a consequence of widening, we end up
with a new shuffle mask which is half the size of the original shuffle mask.

The byte shuffle (pshufb) from test pr24562.ll has a mask of all SM_SentinelZero
indices. Function canWidenShuffleElements would combine each pair of
SM_SentinelZero indices into a single SM_SentinelZero index. So, in a
logarithmic number of steps (4 in this case), the pshufb mask is simplified to
a mask with only one index which is equal to SM_SentinelZero.

Before this patch, function combineX86ShuffleChain wrongly assumed that a mask
of size one is always equivalent to an identity mask. So, the entire shuffle
chain was just folded away as the combined shuffle mask was treated as a no-op
mask.

With this patch we know check if the only element of a combined shuffle mask is
SM_SentinelZero. In case, we propagate a zero vector.

Differential Revision: http://reviews.llvm.org/D13364

llvm-svn: 250027
2015-10-12 11:25:41 +00:00
Zlatko Buljan
f107a3ecb1 Test commit
llvm-svn: 250026
2015-10-12 11:19:40 +00:00
Pawel Bylica
51dcd3d0fd cmake: Avoid leading space in LLVM_DEFINITIONS.
Summary: Unnecessary space at the beginning of LLVM_DEFINITIONS in cmake shared files can break projects that use the variable.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13432

llvm-svn: 250025
2015-10-12 10:42:03 +00:00
Jonas Paulsson
f0275ef824 [SystemZ] testcase MC/SystemZ/insn-good-z13.s extended.
New instructions using floating point registers have been added, to check
that AsmParser can deal with fp regs in vector instructions.

This tests r249810.

llvm-svn: 250023
2015-10-12 10:13:57 +00:00
James Molloy
2ebbfcd5b1 [MISched] Python script to check coverage of misched info
This script prints a CSV of all misched models of a target when given the output of the debug output of subtarget using:

    llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter ...

With thanks to Dave Estes for mentioning the idea at the 2014 LLVM Developers' Meeting.

Patch by Christof Douma!

llvm-svn: 250020
2015-10-12 08:50:47 +00:00
Tobias Grosser
de0082bcae SCEV: Allow simple AddRec * Parameter products in delinearization
This patch also allows the -delinearize pass to delinearize expressions that do
not have an outermost SCEVAddRec expression. The SCEV::delinearize
infrastructure allowed this since r240952, but the -delinearize pass was not
updated yet.

llvm-svn: 250018
2015-10-12 08:02:00 +00:00
Craig Topper
cc35f2e5b6 [X86] Use u8imm for the immediate type for all shift and rotate instructions. This way the assembler will perform range checking. Believe this matches gas behavior.
llvm-svn: 250016
2015-10-12 06:23:10 +00:00
Craig Topper
e7d5502122 [X86] Add support to assembler and MCInst lowering to use the other vmovq %xmmX, %xmmX encoding if it would be a shorter VEX encoding.
llvm-svn: 250014
2015-10-12 04:57:59 +00:00
Craig Topper
e343e59b1b [X86] Cleanup formatting a bit. NFC
llvm-svn: 250013
2015-10-12 04:27:17 +00:00
Craig Topper
18c728de25 [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size.
llvm-svn: 250012
2015-10-12 04:17:55 +00:00
Craig Topper
52829a95cf [X86] Add some instruction aliases to get the assembly parser table to favor arithmetic instructions with 8-bit immediates over the forms that implicitly use the ax/eax/rax.
This allows us to remove the explicit code for working around the existing priority

llvm-svn: 250011
2015-10-12 03:39:57 +00:00
Davide Italiano
35bfd00e5a [llvm-rtdyld] General modernization/cleanup in preparation for (bigger) changes.
llvm-svn: 250004
2015-10-12 00:57:29 +00:00
Davide Italiano
2fa01ffad6 [Bugpoint] Get rid of dead code. No functional change.
llvm-svn: 249999
2015-10-11 21:36:11 +00:00
Craig Topper
192161e032 [X86] Fix CMP and TEST with al/ax/eax/rax to not mark EFLAGS as a use or al/ax/eax/rax as a def. Probably doesn't have a functional affect since these aren't used in isel.
llvm-svn: 249994
2015-10-11 19:54:02 +00:00
Simon Pilgrim
63cbcd050f [DAGCombiner] Improved FMA combine support for vectors
Enabled constant canonicalization for all constants.

Improved combining of constant vectors.

llvm-svn: 249993
2015-10-11 19:48:12 +00:00
Simon Pilgrim
80166fe7b5 [X86] Completed SHL cost model tests
As discussed in D8690. 

llvm-svn: 249990
2015-10-11 18:33:48 +00:00
Craig Topper
7a2aafba5d [X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.
This also fixes a bug where negative immediates below -128 were not being reported as errors.

llvm-svn: 249989
2015-10-11 18:27:24 +00:00
Simon Pilgrim
a4eb4edeaa [X86] Renamed SHL cost model tests
Matches naming conventions for ASHR/LSHR cost tests

As discussed in D8690. 

llvm-svn: 249984
2015-10-11 17:34:32 +00:00
Simon Pilgrim
9d0fcdf692 [X86] Added LSHR cost model tests
There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing.

As discussed in D8690. 

llvm-svn: 249983
2015-10-11 17:29:26 +00:00
Simon Pilgrim
b7a0a2bc2c [X86] Added ASHR cost model tests
There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing.

As discussed in D8690. 

llvm-svn: 249981
2015-10-11 17:08:05 +00:00
Craig Topper
df32bdfb27 [TableGen] Add a space between type and '*' in front of a variable name in output file. While there replace type with 'auto' since there's a cast on the right side of the assignment. NFC
llvm-svn: 249980
2015-10-11 16:59:29 +00:00
Craig Topper
a7582c1073 [X86] Simplify immediate range checking code.
llvm-svn: 249979
2015-10-11 16:38:14 +00:00
Simon Pilgrim
66aee740f0 [DAGCombiner] Tidyup FMINNUM/FMAXNUM constant folding
Enable constant folding for vector splats as well as scalars.

Enable constant canonicalization for all scalar and vector constants.

llvm-svn: 249978
2015-10-11 16:02:28 +00:00
Simon Pilgrim
91bf14e39c [InstCombine][X86][XOP] Combine XOP integer vector comparisons to native IR
We now have lowering support for XOP PCOM/PCOMU instructions.

llvm-svn: 249977
2015-10-11 14:38:34 +00:00
Simon Pilgrim
ebc177d6ad [X86][XOP] Added support for the lowering of 128-bit vector integer comparisons to XOP PCOM/PCOMU instructions.
The XOP vector integer comparisons can deal with all signed/unsigned comparison cases directly and can be easily commuted as well (D7646).

llvm-svn: 249976
2015-10-11 14:15:17 +00:00
Nathan Slingerland
3dad6f16f9 [ProfileData] Test commit for slingn
This is a test of the LLVM commit system. In the event of a real commit there would be some useful code changes.

llvm-svn: 249972
2015-10-11 13:30:56 +00:00
Simon Pilgrim
45d641e674 [X86][SSE] Vector signed/unsigned integer compare tests.
llvm-svn: 249954
2015-10-10 22:21:05 +00:00
Craig Topper
d0338c475c Change isUIntN/isIntN calls with constant N to use the template version. NFC
llvm-svn: 249952
2015-10-10 20:17:07 +00:00
Craig Topper
ce9ae99d64 In isUIntN, make sure N is less than 64 before using in a shift to avoid undefined behavior. Also change it to use the same formula as the template version which I think results in less math in compiled code.
llvm-svn: 249951
2015-10-10 18:54:26 +00:00
Teresa Johnson
959a4588b8 Fix PR25101 - Handle anonymous functions without VST entries
Summary:
The change to use the VST function entries for lazy deserialization did
not handle the case of anonymous functions without aliases. In that case
we must fall back to scanning the function blocks as there is no VST
entry.

Reviewers: dexonsmith, joker.eph, davidxl

Subscribers: tstellarAMD, llvm-commits

Differential Revision: http://reviews.llvm.org/D13596

llvm-svn: 249947
2015-10-10 14:18:36 +00:00
Jonas Paulsson
b352da4d0d [SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs
Relates to the fixes of r249811.

llvm-svn: 249946
2015-10-10 07:20:23 +00:00
Jonas Paulsson
4a28de9033 [SystemZ] Fixes in the backend I/R.
expandPostRAPseudo():
STX -> 2 * STD: The first STD should not have the kill flag set for the address.

SystemZElimCompare:
BRC -> BRCT conversion: Don't forget to remove the CC<use,kill> operand.

Needed to make SystemZ/asm-17.ll pass with -verify-machineinstrs, which
now runs with this flag.

Reviewed by Ulrich Weigand.

llvm-svn: 249945
2015-10-10 07:14:24 +00:00
Sanjoy Das
27d6cafd03 [IndVars] Use auto; NFC
llvm-svn: 249944
2015-10-10 06:33:33 +00:00
Craig Topper
9c3269ab97 Use range-based for loops. NFC
llvm-svn: 249943
2015-10-10 05:38:14 +00:00
Keno Fischer
013ae41096 [RuntimeDyld] Fix performance problem in resolveRelocations with many sections
Summary:
Rather than just iterating over all sections and checking whether we have relocations for them, iterate over the relocation map instead. This showed up heavily in an artificial julia benchmark that does lots of compilation. On that particular benchmark, this patch gives
~15% performance improvements. As far as I can tell the primary reason why the original
loop was so expensive is that Relocations[i] actually constructs a relocationList (allocating memory & doing lots of other unnecessary computing) if none is found.

Reviewers: lhames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13545

llvm-svn: 249942
2015-10-10 05:37:02 +00:00
Craig Topper
ebfe76e532 Use range-based for loops. NFC.
llvm-svn: 249941
2015-10-10 05:25:06 +00:00
Craig Topper
57aa5f153c Use emplace_back instead of a constructor call and push_back. NFC
llvm-svn: 249940
2015-10-10 05:25:02 +00:00
NAKAMURA Takumi
eef812edef Suppress LLVM::tools/llvm-symbolizer/coff-dwarf.test for mingw, for now.
FIXME: Improve llvm-symbolizer, or rename the feature "system-windows".
llvm-svn: 249937
2015-10-10 02:57:02 +00:00
Kostya Serebryany
73cad7579b [libFuzzer] document more trophies
llvm-svn: 249933
2015-10-10 02:14:18 +00:00
Kevin Enderby
42373491ad Move llvm-objdump malformed Mach-O tests to X86 test directory.
rdar://22983603

llvm-svn: 249927
2015-10-10 01:06:20 +00:00
Duncan P. N. Exon Smith
c56daa1083 Analysis: Remove implicit ilist iterator conversions
Remove implicit ilist iterator conversions from LLVMAnalysis.

I came across something really scary in `llvm::isKnownNotFullPoison()`
which relied on `Instruction::getNextNode()` being completely broken
(not surprising, but scary nevertheless).  This function is documented
(and coded to) return `nullptr` when it gets to the sentinel, but with
an `ilist_half_node` as a sentinel, the sentinel check looks into some
other memory and we don't recognize we've hit the end.

Rooting out these scary cases is the reason I'm removing the implicit
conversions before doing anything else with `ilist`; I'm not at all
surprised that clients rely on badness.

I found another scary case -- this time, not relying on badness, just
bad (but I guess getting lucky so far) -- in
`ObjectSizeOffsetEvaluator::compute_()`.  Here, we save out the
insertion point, do some things, and then restore it.  Previously, we
let the iterator auto-convert to `Instruction*`, and then set it back
using the `Instruction*` version:

    Instruction *PrevInsertPoint = Builder.GetInsertPoint();

    /* Logic that may change insert point */

    if (PrevInsertPoint)
      Builder.SetInsertPoint(PrevInsertPoint);

The check for `PrevInsertPoint` doesn't protect correctly against bad
accesses.  If the insertion point has been set to the end of a basic
block (i.e., `SetInsertPoint(SomeBB)`), then `GetInsertPoint()` returns
an iterator pointing at the list sentinel.  The version of
`SetInsertPoint()` that's getting called will then call
`PrevInsertPoint->getParent()`, which explodes horribly.  The only
reason this hasn't blown up is that it's fairly unlikely the builder is
adding to the end of the block; usually, we're adding instructions
somewhere before the terminator.

llvm-svn: 249925
2015-10-10 00:53:03 +00:00
Davide Italiano
8b3ac7fec5 [llvm-rtdyld] Use range-based loop. NFC.
llvm-svn: 249923
2015-10-10 00:45:24 +00:00
Duncan P. N. Exon Smith
1364b6b382 MC: Remove implicit ilist iterator conversions, NFC
llvm-svn: 249922
2015-10-10 00:13:11 +00:00
Kevin Enderby
ad8640ff94 Fix a bugs in the Mach-O disassembler when disassembling from a
malformed Mach-O file that caused a crash.  This was because of an
assert where the code was incorrectly attempting to parse relocation
entries off of the sections and the filetype was not an MH_OBJECT.

rdar://22983603

llvm-svn: 249921
2015-10-10 00:05:01 +00:00
David Majnemer
731d894ca2 [WinEH] Remove more dead code
wineh-parent is dead, so is ValueOrMBB.

llvm-svn: 249920
2015-10-10 00:04:29 +00:00
Reid Kleckner
51ced6582b [WinEH] Delete the old landingpad implementation of Windows EH
The new implementation works at least as well as the old implementation
did.

Also delete the associated preparation tests. They don't exercise
interesting corner cases of the new implementation. All the codegen
tests of the EH tables have already been ported.

llvm-svn: 249918
2015-10-09 23:34:53 +00:00
Reid Kleckner
fbc7540bf7 [SEH] Update SEH codegen tests to use the new IR
Also Fix a buglet where SEH tables had ranges that spanned funclets.

The remaining tests using the old landingpad IR are preparation tests,
and will be deleted along with the old preparation.

llvm-svn: 249917
2015-10-09 23:05:54 +00:00