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Commit Graph

214508 Commits

Author SHA1 Message Date
Nico Weber
25b1225bca [Support] Don't include VirtualFileSystem.h in CommandLine.h
CommandLine.h is indirectly included in ~50% of TUs when building
clang, and VirtualFileSystem.h is large.

(Already remarked by jhenderson on D70769.)

No behavior change.

Differential Revision: https://reviews.llvm.org/D100957
2021-04-21 10:19:01 -04:00
Simon Pilgrim
2f6d5a3c21 [PhaseOrdering] Add test case for PR45682
Ensures that the correct sequence of simplifycfg/instcombine/sroa reduce the IR to just a icmp+assume (which will be dropped in backend)
2021-04-21 15:07:00 +01:00
Simon Pilgrim
4edb18ca2b [MC] MCInstrDesc.h - remove unnecessary <string> include. NFCI. 2021-04-21 15:07:00 +01:00
Fraser Cormack
3d3fa3ed76 [SelectionDAG] Fix minor typo in ISDOpcodes.h. NFC 2021-04-21 14:38:07 +01:00
Caroline Concatto
547af41fa3 [AArch64][SVE] Fix crash with icmp+select
This patch changes the lowering of SELECT_CC from Legal to Expand for scalable
vector and adds support for scalable vectors in performSelectCombine.

When selecting the nodes to lower in visitSELECT it checks if it is possible to
use SELECT_CC in cases where SETCC is followed by SELECT. visistSELECT checks
if SELECT_CC is legal or custom to replace SELECT by SELECT_CC.
SELECT_CC used to be legal for scalable vector, so the node changes to
SELECT_CC. This used to crash the compiler as there is no support for SELECT_CC
with scalable vectors. So now the compiler lowers to VSELECT instead of
SELECT_CC.

Differential Revision: https://reviews.llvm.org/D100485
2021-04-21 14:16:27 +01:00
Matt Arsenault
4fb212a574 AMDGPU: Fix indirect tail calls
Fix a selection error on uniform callees, and use a regular call if
divergent.
2021-04-21 09:15:24 -04:00
David Green
118f1ecde3 [AArch64] Add and update reverse mask tests. NFC 2021-04-21 12:11:41 +01:00
Simon Tatham
49b1d59516 [ARM][Driver][Windows] Allow command-line upgrade to Armv8.
If you gave clang the options `--target=arm-pc-windows-msvc` and
`-march=armv8-a+crypto` together, the crypto extension would not be
enabled in the compilation, and you'd see the following warning
message suggesting that the 'armv8-a' had been ignored:

  clang: warning: ignoring extension 'crypto' because the 'armv7-a' architecture does not support it [-Winvalid-command-line-argument]

This happens because Triple::getARMCPUForArch(), for the Win32 OS,
unconditionally returns "cortex-a9" (an Armv7 CPU) regardless of
MArch, which overrides the architecture setting on the command line.

I don't think that the combination of Windows and AArch32 _should_
unconditionally outlaw the use of the crypto extension. MSVC itself
doesn't think so: you can perfectly well compile Thumb crypto code
using its AArch32-targeted compiler.

All the other default CPUs in the same switch statement are
conditional on a particular MArch setting; this is the only one that
returns a particular CPU _regardless_ of MArch. So I've fixed this one
by adding a condition, so that if you ask for an architecture *above*
v7, the default of Cortex-A9 no longer overrides it.

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D100937
2021-04-21 11:20:05 +01:00
Simon Pilgrim
2a2d25a7be [DAG] TargetLowering.cpp - breakup if-else chains where each block returns. NFCI.
Match style guide that requests that if+return blocks are separate.
2021-04-21 11:17:27 +01:00
Fraser Cormack
74ffc8e63c [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines
This patch adds incrementally-better support for SPLAT_VECTOR in a
handful of vector combines by changing a few more
isBuildVectorAllOnes/isBuildVectorAllZeros to the equivalent
isConstantSplatVectorAllOnes/Zeros calls.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D100851
2021-04-21 11:05:37 +01:00
Fraser Cormack
95fc7ab21d [RISCV] Further fixes for RVV stack offset computation
This patch fixes a case missed out by D100574, in which RVV scalable
stack offset computations may require three live registers in the case
where the offset's fixed component is 12 bits or larger and has a
scalable component.

Instead of adding an additional emergency spill slot, this patch further
optimizes the scalable stack offset computation sequences to reduce
register usage.

By emitting the sequence to compute the scalable component before the
fixed component, we can free up one scratch register to be reallocated
by the sequence for the fixed component. Doing this saves one register
and thus one additional emergency spill slot.

Compare:

    $x5 = LUI 1
    $x1 = ADDIW killed $x5, -1896
    $x1 = ADD $x2, killed $x1
    $x5 = PseudoReadVLENB
    $x6 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x6
    $x1 = ADD killed $x1, killed $x5

versus:

    $x5 = PseudoReadVLENB
    $x1 = ADDI $x0, 50
    $x5 = MUL killed $x5, killed $x1
    $x1 = LUI 1
    $x1 = ADDIW killed $x1, -1896
    $x1 = ADD $x2, killed $x1
    $x1 = ADD killed $x1, killed $x5

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100847
2021-04-21 10:51:07 +01:00
Martin Storsjö
4a1d40cba0 [llvm-rc] Try to fix the Preprocessor/llvm-rc.rc test on non arm/x86 architectures
When llvm-rc invokes clang for preprocessing, it uses a target
triple derived from the default target. The test verifies that
e.g. _WIN32 is defined when preprocessing.

If running clang with e.g. -target ppc64le-windows-msvc, that
particular arch/OS combination isn't hooked up, so _WIN32 doesn't
get defined in that configuration. Therefore, the preprocessing
test fails.

Instead make llvm-rc inspect the architecture of the default target.
If it's one of the known supported architectures, use it as such,
otherwise set a default one (x86_64). (Clang can run preprocessing
with an x86_64 target triple, even if the x86 backend isn't
enabled.)

Also remove superfluous llvm:: specifications on enums in llvm-rc.cpp.
2021-04-21 12:47:33 +03:00
Martin Storsjö
ae24723f0f [llvm-rc] Run clang to preprocess input files
Allow opting out from preprocessing with a command line argument.

Update tests to pass -no-preprocess to make it not try to use clang
(which isn't a build level dependency of llvm-rc), but add a test that
does preprocessing under clang/test/Preprocessor.

Update a few options to allow them both joined (as -DFOO) and separate
(-D BR), as rc.exe allows both forms of them.

With the verbose flag set, this prints the preprocessing command
used (which differs from what rc.exe does).

Tests under llvm/test/tools/llvm-rc only test constructing the
preprocessor commands, while tests under clang/test/Preprocessor test
actually running the preprocessor.

Differential Revision: https://reviews.llvm.org/D100755
2021-04-21 11:50:10 +03:00
Martin Storsjö
09f1330345 [llvm-cvtres] Reduce the set of dependencies of llvm-cvtres. NFC.
Don't use createBinary() but call the WindowsResource class directly.
The createBinary() function references all supported object file
types and ends up pulling way more from all the underlying libraries
than what is necessary.

This shrinks a stripped llvm-cvtres from 4.6 MB to 463 KB.

Differential Revision: https://reviews.llvm.org/D100833
2021-04-21 11:50:10 +03:00
David Sherwood
081c5cd9a4 [AArch64] Add instruction costs for FP_TO_UINT and FP_TO_SINT with half types
We were missing some instruction costs when converting vectors of
floating point half types into integers, so I've added those here.
I also manually generated assembly code for each FP->int case and
looked at the number of instructions generated, which meant
adjusting some of the existing costs too.

I've updated an existing test to reflect the new costs:

  Analysis/CostModel/AArch64/sve-fptoi.ll

Differential Revision: https://reviews.llvm.org/D99935
2021-04-21 09:39:45 +01:00
Christian Kühnel
a6b448f809 [NFC] fixed link in documentation 2021-04-21 10:17:03 +02:00
Yang Fan
0c89a953db [SCEV] Fix -Wunused-variable warning (NFC)
GCC warning:
```
/llvm-project/llvm/lib/Analysis/ScalarEvolution.cpp: In member function ‘const llvm::SCEV* llvm::ScalarEvolution::getLosslessPtrToIntExpr(const llvm::SCEV*, unsigned int)::SCEVPtrToIntSinkingRewriter::visitUnknown(const llvm::SCEVUnknown*)’:
/llvm-project/llvm/lib/Analysis/ScalarEvolution.cpp:1152:13: warning: unused variable ‘ExprPtrTy’ [-Wunused-variable]
 1152 |       Type *ExprPtrTy = Expr->getType();
      |             ^~~~~~~~~
```
2021-04-21 16:01:46 +08:00
Christian Kühnel
271e47c106 added section on CI system
Add documentation for working with the CI systems.

This is based on the discussion in the Infrastructure Working Group:
https://github.com/ChristianKuehnel/iwg-workspace/issues/37

Differential Revision: https://reviews.llvm.org/D97389
2021-04-21 09:59:41 +02:00
Nikita Popov
f8a60b9733 Revert "[InstSimplify] Bypass no-op and-mask, using known bits (PR49543)"
This reverts commit ea1a0d7c9ae3e5232a4163fc67efad4aabd51f2b.

While this is strictly more powerful, it is also strictly slower.
InstSimplify intentionally does not perform many folds that it
is allowed to perform, if doing so requires a KnownBits calculation
that will be repeated in InstCombine.

Maybe it's worthwhile to do this here, but that needs a more
explicitly stated motivation, evaluated in a review.
2021-04-21 09:55:25 +02:00
David Sherwood
1ea67899d6 [Docs] Fix formatting issue for llvm.experimental.stepvector in LangRef
The llvm.experimental.stepvector section was missing the '^^^' line
underneath the intrinsic name.
2021-04-21 08:42:40 +01:00
Zakk Chen
d233144dbc [RISCV][MC] Mask load should not have VMConstraint.
Add a test, dest register could be v0.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D100825
2021-04-21 15:21:37 +08:00
Serge Pavlov
72eb7a3974 [RISCV] Introduce floating point control and state registers
New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.

Differential Revision: https://reviews.llvm.org/D99083
2021-04-21 12:55:30 +07:00
serge-sans-paille
0241a57a8c Use SmallVector instead of std::vector to manage storage of llvm::BitVector
This is a follow-up to https://reviews.llvm.org/D100387.

std::vector is not the best storage container here. My local benchmark (counting
the number of instruction when compiling the sqlite3 amalgamation) yields the
following:

- std::vector<BitVector> -> 5,860,885,896
- SmallVector<BitWord, 0> -> 5,858,991,997
- SmallVector<BitWord> -> 5,817,679,224

Differential Revision: https://reviews.llvm.org/D100744
2021-04-21 07:31:28 +02:00
Arthur Eubanks
fa90b27f77 [NFC] Remove redundant InstCombinePass name 2021-04-20 22:23:07 -07:00
Max Kazantsev
1c29570e8c [Test] Add a negative unit test 2021-04-21 12:11:05 +07:00
Zi Xuan Wu
844e8b7b70 [NFC][CSKY] Resort the instruction description in td
Resort the instruction description in td to make it easy to upstream more instructions and add predicts later.
2021-04-21 12:36:07 +08:00
Craig Topper
550007c220 [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC 2021-04-20 18:31:36 -07:00
George Balatsouras
8eaf3e2f22 [dfsan] Enable origin tracking with fast8 mode
All related instrumentation tests have been updated.

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D100903
2021-04-20 18:10:32 -07:00
Adrian Prantl
2f75daf38f Make sure PHIElimination doesn't copy debug locations across basic blocks.
PHIElimination may insert copy instructions in multiple basic
blocks. Moving debug locations across basic block boundaries would be
misleading as illustrated by the test case.

rdar://75463656

Differential Revision: https://reviews.llvm.org/D100886
2021-04-20 17:03:29 -07:00
Sam Clegg
7d3fbb9953 [WebAssembly] Update README. NFC.
This is just a cleanup of the very high level stuff.  I'm sure there is
more to update here but I'll leave that to others and/or a followup.

Differential Revision: https://reviews.llvm.org/D100888
2021-04-20 16:59:08 -07:00
Arthur Eubanks
4cb445df42 [FuncAttrs] Always preserve FunctionAnalysisManagerCGSCCProxy
FunctionAnalysisManagerCGSCCProxy should not be preserved if any of its
keys may be invalid. Since we are not removing/adding functions in
FuncAttrs, it's fine to preserve it.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D100893
2021-04-20 16:37:45 -07:00
Jim Radford
59805704ed [CMake][llvm] avoid changing global flags (may be used outside of llvm)
Changing global flags can break builds of projects that include/build
llvm as a sub-project, as the effect is global. Ideally we would
disable this warning at the directory level instead, but the obvious
way (disabling warning D9025) isn't supported. At least we can limit
the effect to only MSVC.

Patch by Jim Radford.

Differential Revision: https://reviews.llvm.org/D100900
2021-04-20 16:06:25 -07:00
Reid Kleckner
9055783420 Revert "[InstCombine] Recognize ((x * y) s/ x) !=/== y as an signed multiplication overflow check (PR48769)"
This reverts commit 13ec913bdf500e2354cc55bf29e2f5d99e0c709e.

This commit introduces new uses of the overflow checking intrinsics that
depend on implementations in compiler-rt, which Windows users generally
do not link against. I filed an issue (somewhere) to make clang
auto-link the builtins library to resolve this situation, but until that
happens, it isn't reasonable for the optimizer to introduce new link
time dependencies.
2021-04-20 15:53:34 -07:00
Philip Reames
5209f18c1c Revert "Allow invokable sub-classes of IntrinsicInst"
This reverts commit d87b9b81ccb95217181ce75515c6c68bbb408ca4.

Post commit review raised concerns, reverting while discussion happens.
2021-04-20 15:38:38 -07:00
Roman Lebedev
2608e4a8c5 Revert "[InstCombine] sext(trunc(x)) --> sext(x) iff trunc is NSW (PR49543)"
I forgot about the case where we sign-extend to width smaller than the original.

This reverts commit 1e6ca23ab8e350c7bab5d7f93e4d3dee18d180cc.
2021-04-21 01:11:15 +03:00
Roman Lebedev
3c5afdb7f4 Revert "[InstCombine] "Bypass" NUW trunc of lshr if we are going to sext the result (PR49543)"
I forgot about the case where we sign-extend to width smaller than the original.

This reverts commit 41b71f718b94c6f12bbaa670e97cabb070308ed2.
2021-04-21 01:11:14 +03:00
Philip Reames
4f3ea7d288 Allow invokable sub-classes of IntrinsicInst
It used to be that all of our intrinsics were call instructions, but over time, we've added more and more invokable intrinsics. According to the verifier, we're up to 8 right now. As IntrinsicInst is a sub-class of CallInst, this puts us in an awkward spot where the idiomatic means to check for intrinsic has a false negative if the intrinsic is invoked.

This change switches IntrinsicInst from being a sub-class of CallInst to being a subclass of CallBase. This allows invoked intrinsics to be instances of IntrinsicInst, at the cost of requiring a few more casts to CallInst in places where the intrinsic really is known to be a call, not an invoke.

After this lands and has baked for a couple days, planned cleanups:
    Make GCStatepointInst a IntrinsicInst subclass.
    Merge intrinsic handling in InstCombine and use idiomatic visitIntrinsicInst entry point for InstVisitor.
    Do the same in SelectionDAG.
    Do the same in FastISEL.

Differential Revision: https://reviews.llvm.org/D99976
2021-04-20 15:03:49 -07:00
Roman Lebedev
d798143ee1 [InstCombine] "Bypass" NUW trunc of lshr if we are going to sext the result (PR49543)
This is a more convoluted form of the same pattern "sext of NSW trunc",
but in this case the operand of trunc was a right-shift,
and the truncation chops off just the zero bits that were shifted-in.
2021-04-21 00:31:46 +03:00
Roman Lebedev
aaf0143de8 [NFC][InstCombine] Add tests for sext-of-trunc-nuw-of-lshr (PR49543) 2021-04-21 00:31:46 +03:00
Roman Lebedev
b7b50a3bdd [InstSimplify] Bypass no-op and-mask, using known bits (PR49543)
We already special-cased a few interesting patterns,
but that is strictly less powerful than using KnownBits.

So instead get the known bits for the operand of `and`,
and iff all the unset bits of the `and`-mask are known to be zeros
in the operand, we can omit said `and`.
2021-04-21 00:31:46 +03:00
Roman Lebedev
aaf316266e [NFC][InstSimplify] Add one more test for unneeded 'and' 2021-04-21 00:31:46 +03:00
Roman Lebedev
23c15f2a2e [InstCombine] sext(trunc(x)) --> sext(x) iff trunc is NSW (PR49543)
If we can tell that trunc only chops off sign bits, and not all of them,
then we can simply sign-extend the trunc's source.
2021-04-21 00:31:45 +03:00
Roman Lebedev
1d861cd268 [NFC][InstCombine] Add test for sign-extending NSW trunc (PR49543) 2021-04-21 00:31:45 +03:00
Sanjay Patel
89c1a36077 [InstCombine] fold shift-of-srem-by-2 to mask+shift
There are several potential srem-by-2 folds
because the result is known {-1,0,1}.

https://alive2.llvm.org/ce/z/LuVyeK
2021-04-20 17:10:16 -04:00
Sanjay Patel
b16c2ede3c [InstCombine] add tests for srem-by-2; NFC 2021-04-20 17:10:16 -04:00
Sam Clegg
8c8f002458 [WebAssembly] Remove unused known_gcc_test_failures.txt. NFC
Differential Revision: https://reviews.llvm.org/D100887
2021-04-20 14:07:25 -07:00
Alexey Bataev
907c8ed010 [COST][AARCH64] Improve cost of reverse shuffles for AArch64.
Introduced the cost of thre reverse shuffles for AArch64, currently just
copied the costs for PermuteSingleSrc.

Differential Revision: https://reviews.llvm.org/D100871
2021-04-20 13:47:56 -07:00
Philip Reames
6215df8065 Reapply "Look through invertible recurrences in isKnownNonEqual"
I'd reverted this in commit 3b6acb179708ea2f3caf95ace0f134fcbc460333 due to buildbot failures.  This patch contains the fix for said issue.  I'd forgotten to handle the case where two phis in the same block have different operand order.  We canonicalize away from this, but it's still valid IR.  The tests included in this change (as opposed to simply having test output changed), crashed without the fix.

Original commit message follows...

This extends the phi handling in isKnownNonEqual with a special case based on invertible recurrences. If we can prove the recurrence is invertible (which many common ones are), we can recurse through the start operands of the recurrence skipping the phi cycle.

(Side note: Instcombine currently does not push back through these cases. I will implement that in a follow up change w/separate review.)

Differential Revision: https://reviews.llvm.org/D99912
2021-04-20 12:47:59 -07:00
Jon Roelofs
5807e188d1 [AArch64][GlobalISel] Clarify fallback debug print
... to only print when that fallback actually happens.
2021-04-20 12:41:14 -07:00
Thomas Lively
1844c2454c [WebAssembly] More codegen for f64x2.convert_low_i32x4_{s,u}
af7925b4dd65 added a custom DAG combine for recognizing fp-to-ints of
extract_subvectors that could be lowered to f64x2.convert_low_i32x4_{s,u}
instructions. This commit extends the combines to recognize equivalent
extract_subvectors of fp-to-ints as well.

Differential Revision: https://reviews.llvm.org/D100790
2021-04-20 12:37:13 -07:00