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Commit Graph

21 Commits

Author SHA1 Message Date
Chris Lattner
9185c43c7d make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
llvm-svn: 48118
2008-03-09 20:12:44 +00:00
Bill Wendling
2cae66e28b Final de-tabification.
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
2007-11-11 19:50:10 +00:00
Chris Lattner
db290f7479 Constify some methods. Patch provided by Anton Vayvod, thanks!
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
Jim Laskey
1716e53341 Add dwarf register numbering to register data.
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
Duraid Madina
f868d1777b fix stack corruption! Previously, 16-byte whole-FP-register stores were
being treated as needing only 8 bytes (though they were 16 byte aligned.)

This should fix a bunch of tests - anyone have any comments, though?

  - in Target.td , SpillSize and SpillAlignment seem dead - is this what
    Size and Alignment do now?
  - in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
    DeclaredSpillAlignment seem dead.
  - there are a bunch of comments here and there that don't clearly
    distinguish between 'size' and 'spillsize' etc. hmm.

llvm-svn: 25644
2006-01-26 09:45:03 +00:00
Duraid Madina
43e8616515 fix register corruption! (my god.) r15 is a scratch reg, using that as
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!

llvm-svn: 25526
2006-01-23 06:08:46 +00:00
Duraid Madina
365cb4f82d use proper (82-bit) spills/fills when spilling FP regs, so that
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)

llvm-svn: 25385
2006-01-17 02:04:52 +00:00
Duraid Madina
2c940da498 update tablegen files - nothing to see here
llvm-svn: 24939
2005-12-22 03:56:03 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.

llvm-svn: 24563
2005-12-01 04:51:06 +00:00
Duraid Madina
e89d6f5197 add F0 and F1 to the FP register class
llvm-svn: 24151
2005-11-02 07:30:39 +00:00
Duraid Madina
251185e626 DAG->DAG instruction selection for ia64! "hello world" works, not much else.
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.

llvm-svn: 24058
2005-10-28 17:46:35 +00:00
Chris Lattner
2ac3fd08d2 Split RegisterClass 'Methods' into MethodProtos and MethodBodies
llvm-svn: 22929
2005-08-19 19:13:20 +00:00
Chris Lattner
9d61d4a3e4 Put register classes in namespaces
llvm-svn: 22924
2005-08-19 18:50:46 +00:00
Duraid Madina
39fcec1541 * OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252
2005-04-12 18:42:59 +00:00
Chris Lattner
be2dceff48 Put out* into the allocation order, allowing the register allocator to
coallesce moves into outgoing args.

llvm-svn: 21249
2005-04-12 15:12:51 +00:00
Duraid Madina
2821f99f19 stop emitting IDEFs for args - change to using liveIn/liveOut
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
Duraid Madina
2d3e52576d ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.

llvm-svn: 21178
2005-04-09 11:53:00 +00:00
Duraid Madina
62c4de8d62 make sure 'special' registers don't get allocated
llvm-svn: 21109
2005-04-06 06:17:54 +00:00
Duraid Madina
79022e1b87 and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!

llvm-svn: 20652
2005-03-17 18:17:03 +00:00