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Author SHA1 Message Date
Craig Topper
26f41cda03 Add X86ISD::HADD/HSUB to getTargetNodeName 
llvm-svn: 145929
 2011-12-06 09:31:36 +00:00
Craig Topper
8b05e7d035 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
llvm-svn: 145927
 2011-12-06 09:04:59 +00:00
Craig Topper
846d53deed Merge floating point and integer UNPCK X86ISD node types. 
llvm-svn: 145926
 2011-12-06 08:21:25 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
 2011-12-06 06:48:26 +00:00
Craig Topper
e6e44c24dd Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs. 
llvm-svn: 145924
 2011-12-06 05:31:16 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Craig Topper
72b41227d8 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
llvm-svn: 145921
 2011-12-06 04:59:07 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

llvm-svn: 145916
 2011-12-06 03:56:05 +00:00
Dan Gohman
02bdcdd326 Fix a subtle semantic issue with poison values that came up in 
recent discussions. Poison can't make every value that depends on
it act in maximally undefined ways, because the optimizer may still
hoist code following the usual rules for undef. Make Poison invoke
its full undefined behavior only when it reaches an instruction with
externally visible side effects.

llvm-svn: 145913
 2011-12-06 03:35:58 +00:00
Bruno Cardoso Lopes
6739e47b15 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
llvm-svn: 145912
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes
379e4c7a14 Explicit symbols for gnu mimicing relocations. Patch by Jack Carter 
llvm-svn: 145911
 2011-12-06 03:34:42 +00:00
Bruno Cardoso Lopes
4638d36bd2 Add register HWR29 numbering. Patch by Jack Carter 
llvm-svn: 145910
 2011-12-06 03:34:36 +00:00
Dan Gohman
7d881a178c Line up the comments in a code example. 
llvm-svn: 145908
 2011-12-06 03:31:14 +00:00
Dan Gohman
db3a5dbdb5 Rename "Trap Values" to "Poison Values", to better reflect their 
purpose, and to avoid ambiguity with other uses of the word "trap"
in LangRef.

llvm-svn: 145907
 2011-12-06 03:18:47 +00:00
Andrew Trick
04c98888bc LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.

llvm-svn: 145906
 2011-12-06 03:13:31 +00:00
Evan Cheng
91ae428cc0 Mix some minor misuse of MachineBasicBlock iterator. 
llvm-svn: 145903
 2011-12-06 02:49:06 +00:00
Pete Cooper
61ffb8fcc5 Removed isWinToJoinCrossClass from the register coalescer. 
The new register allocator is much more able to split back up ranges too constrained by register classes.

Fixes <rdar://problem/10466609>

llvm-svn: 145899
 2011-12-06 02:06:50 +00:00
Chris Lattner
edb34dd40a allow TinyPtrVector to implicitly convert to ArrayRef. 
llvm-svn: 145898
 2011-12-06 02:00:33 +00:00
Lang Hames
a7f56028f8 Kill off the LoopSplitter. It's not being used or maintained. 
llvm-svn: 145897
 2011-12-06 01:57:59 +00:00
Bill Wendling
e7c74617e5 Add a comment. 
llvm-svn: 145896
 2011-12-06 01:57:48 +00:00
Jim Grosbach
4aba5ca564 Tidy up value checking. 
llvm-svn: 145895
 2011-12-06 01:53:17 +00:00
NAKAMURA Takumi
c626e04fa2 MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc. 
llvm-svn: 145894
 2011-12-06 01:48:32 +00:00
Lang Hames
29572733bb Update PBQP's analysis usage to reflect the requirements of the inline spiller. 
llvm-svn: 145893
 2011-12-06 01:45:57 +00:00
Chad Rosier
70dd1f98af [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
af85f53dd0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Jakob Stoklund Olesen
e53ed273d9 Use logarithmic units for basic block alignment. 
This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889
 2011-12-06 01:26:19 +00:00
Bill Wendling
6e3adcc60a The compact encoding of the registers are 3-bits each. Make sure we shift the 
value over that much.

llvm-svn: 145888
 2011-12-06 01:26:14 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen
e60dea48ec Use an existing function. 
llvm-svn: 145883
 2011-12-06 00:51:12 +00:00
Jakob Stoklund Olesen
faa1b18b38 Fix unclear wording. 
llvm-svn: 145882
 2011-12-06 00:51:09 +00:00
Jim Grosbach
633ce3426c Move target-specific logic out of generic MCAssembler. 
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881
 2011-12-06 00:47:03 +00:00
Nick Lewycky
d59dcc5ddb Expose a switch for the new gcov format. 
llvm-svn: 145880
 2011-12-06 00:29:13 +00:00
Chad Rosier
7096fea51c Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

llvm-svn: 145879
 2011-12-06 00:19:08 +00:00
Jim Grosbach
c3c8c0eddd Tidy up. Hard tabs. 
llvm-svn: 145878
 2011-12-06 00:13:09 +00:00
Jim Grosbach
c13dbd8744 Tidy up. Hard tabs. 
llvm-svn: 145877
 2011-12-06 00:12:12 +00:00
Nick Lewycky
6c5ac27dec All these arguments are default anyways. 
llvm-svn: 145876
 2011-12-06 00:11:58 +00:00
Jim Grosbach
5b567d6669 Tidy up. 80 columns. 
llvm-svn: 145875
 2011-12-06 00:11:13 +00:00
Jim Grosbach
93874e36fa Switch MCAssembler to method names starting w/ lower-case. 
per http://llvm.org/docs/CodingStandards.html#ll_naming

llvm-svn: 145873
 2011-12-06 00:03:48 +00:00
Jim Grosbach
fe71651f99 Simple branch relaxation for Thumb2 Bcc instructions. 
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871
 2011-12-05 23:45:46 +00:00
Jim Grosbach
9112c6a3ee Tidy up. 
llvm-svn: 145870
 2011-12-05 23:20:14 +00:00
Nick Lewycky
389fa6c38d Silence tsan false-positives (tsan can't track things which are only safe due to 
memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.

llvm-svn: 145869
 2011-12-05 23:07:05 +00:00
Chad Rosier
4f8c6f6a9c Update comment. 
llvm-svn: 145866
 2011-12-05 22:53:09 +00:00
Chad Rosier
c50cbc5a65 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

llvm-svn: 145865
 2011-12-05 22:37:00 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Jim Grosbach
898ab7e4ec Thumb2 prefer ADD register encoding T2 to T3 when possible. 
rdar://10529664

llvm-svn: 145860
 2011-12-05 22:16:39 +00:00
Bill Wendling
77e127d56f Move 'returns_twice' definition into alphabetical place. 
llvm-svn: 145854
 2011-12-05 21:27:54 +00:00
Akira Hatanaka
bdefd49aa5 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00