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2730b7865e
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8608 Commits

Author SHA1 Message Date
Michael Liao
2730b7865e Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArith 
- Merge the processing of LOAD_ADD with other atomic load-arith
  operations
- Separate the logic getting target constant for atomic-load-op and add
  an optimization for atomic-load-add on i16 with negative value
- Optimize a minor case for atomic-fetch-add i16 with negative operand. Test
  case is revised.

llvm-svn: 164243
 2012-09-19 19:36:58 +00:00
Craig Topper
abbf768c15 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper
7c37abcace Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit. 
llvm-svn: 164202
 2012-09-19 06:06:34 +00:00
Roman Divacky
e91b4521bf When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.

Fixes PR11212.

llvm-svn: 164132
 2012-09-18 16:08:49 +00:00
Jan Wen Voung
bd8575d1d7 Add some cases to x86 OptimizeCompare to handle DEC and INC, too. 
While we are setting the earlier def to true, also make it live.

llvm-svn: 164056
 2012-09-17 22:04:23 +00:00
Benjamin Kramer
2844c979a6 LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused function warnings use LLVM_ATTRIBUTE_UNUSED. 
llvm-svn: 164036
 2012-09-17 16:46:22 +00:00
Nadav Rotem
c790bc0984 The PMOVZXWD family of functions had patterns extends narrow vector types to wide vector types. 
It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast,
and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics.

rdar://11897677

llvm-svn: 163995
 2012-09-16 07:39:07 +00:00
Craig Topper
95869a202b Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 
llvm-svn: 163974
 2012-09-15 17:09:36 +00:00
Benjamin Kramer
3be8d89f89 X86: Emitting x87 fsin/fcos for sinf/cosf is not safe without unsafe fp math. 
This was only an issue if sse is disabled.

llvm-svn: 163967
 2012-09-15 12:44:27 +00:00
Dmitri Gribenko
93c7ec80b7 Fix Doxygen issues: 
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
  with the rest of the codebase.

llvm-svn: 163902
 2012-09-14 14:57:36 +00:00
Michael Liao
5eea004951 Fix comment 
llvm-svn: 163835
 2012-09-13 20:30:16 +00:00
Michael Liao
0c0da113c5 Add wider vector/integer support for PR12312 
- Enhance the fix to PR12312 to support wider integer, such as 256-bit
  integer. If more than 1 fully evaluated vectors are found, POR them
  first followed by the final PTEST.

llvm-svn: 163832
 2012-09-13 20:24:54 +00:00
Jakob Stoklund Olesen
72138019a9 Fix the TCRETURNmi64 bug differently. 
Add a PatFrag to match X86tcret using 6 fixed registers or less. This
avoids folding loads into TCRETURNmi64 using 7 or more volatile
registers.

<rdar://problem/12282281>

llvm-svn: 163819
 2012-09-13 18:31:27 +00:00
Jakob Stoklund Olesen
eae8fc91cf Revert r163761 "Don't fold indexed loads into TCRETURNmi64." 
The patch caused "Wrong topological sorting" assertions.

llvm-svn: 163810
 2012-09-13 16:52:17 +00:00
Craig Topper
e2e98bb26b Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. 
llvm-svn: 163774
 2012-09-13 05:45:42 +00:00
Jakob Stoklund Olesen
b15912aafd Don't fold indexed loads into TCRETURNmi64. 
We don't have enough GR64_TC registers when calling a varargs function
with 6 arguments. Since %al holds the number of vector registers used,
only %r11 is available as a scratch register.

This means that addressing modes using both base and index registers
can't be folded into TCRETURNmi64.

<rdar://problem/12282281>

llvm-svn: 163761
 2012-09-13 00:25:00 +00:00
Michael Liao
e600a8a616 Fix PR11985 
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.

llvm-svn: 163743
 2012-09-12 21:43:09 +00:00
Chad Rosier
e57a278d0d [ms-inline asm] Make the operand size directives case insensitive. 
llvm-svn: 163729
 2012-09-12 18:24:26 +00:00
Roman Divacky
a811b158e5 Add support for AMD Geode. 
llvm-svn: 163710
 2012-09-12 14:36:02 +00:00
Craig Topper
24d6cafc79 Indentation fixes. No functional change. 
llvm-svn: 163682
 2012-09-12 06:20:41 +00:00
Manman Ren
1a047422a0 Release build: guard dump functions with 
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.

llvm-svn: 163653
 2012-09-11 22:23:19 +00:00
Chad Rosier
c778c0a3f4 StringSwitchify. 
llvm-svn: 163649
 2012-09-11 21:10:25 +00:00
Chad Rosier
e7a6502bbe Simplify logic. No functional change intended. 
llvm-svn: 163648
 2012-09-11 20:57:04 +00:00
Craig Topper
557b8a5a81 Make a bunch of lowering helper functions static instead of member functions. No functional change. 
llvm-svn: 163596
 2012-09-11 06:15:32 +00:00
Craig Topper
c9fd7a1602 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
llvm-svn: 163594
 2012-09-11 04:19:21 +00:00
Chad Rosier
419fa9e0b0 Update function names to conform to guidelines. No functional change intended. 
llvm-svn: 163561
 2012-09-10 22:50:57 +00:00
Chad Rosier
3758eb20e1 Revert r163556. Missed updates to tablegen files. 
llvm-svn: 163557
 2012-09-10 22:30:35 +00:00
Chad Rosier
8bbcf2b7ae Update function names to conform to guidelines. No functional change intended. 
llvm-svn: 163556
 2012-09-10 22:23:45 +00:00
Dmitri Gribenko
1d75adbbb2 Remove redundant semicolons which are null statements. 
llvm-svn: 163547
 2012-09-10 21:26:47 +00:00
Chad Rosier
054e489dd3 [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() function 
and update the printOperand() function accordingly.

llvm-svn: 163544
 2012-09-10 21:10:49 +00:00
Chad Rosier
e1355ead98 [ms-inline asm] Add support for .att_syntax directive. 
llvm-svn: 163542
 2012-09-10 20:54:39 +00:00
Michael Liao
7dfa5e2092 Enhance PR11334 fix to support extload from v2f32/v4f32 
- Fix an remaining issue of PR11674 as well

llvm-svn: 163528
 2012-09-10 18:33:51 +00:00
Michael Liao
2791a08d7e Add boolean simplification support from CMOV 
- If a boolean value is generated from CMOV and tested as boolean value,
  simplify the use of test result by referencing the original condition.
  RDRAND intrinisc is one of such cases.

llvm-svn: 163516
 2012-09-10 16:36:16 +00:00
Elena Demikhovsky
56cdc6a59a The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer. 
I've added the "zeroinitializer" case in this patch.

llvm-svn: 163506
 2012-09-10 12:13:11 +00:00
Nick Lewycky
ad25150d03 Add missing space before {. No functionality change. 
llvm-svn: 163484
 2012-09-09 23:40:55 +00:00
Craig Topper
a91d731898 Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled. 
llvm-svn: 163473
 2012-09-08 17:42:27 +00:00
Craig Topper
9bda7e421e Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering. 
llvm-svn: 163463
 2012-09-08 07:46:05 +00:00
Craig Topper
53ec08b4fc Add support for lowering FABS of vector types. 
llvm-svn: 163461
 2012-09-08 07:31:51 +00:00
Craig Topper
eb1db45675 Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. 
llvm-svn: 163458
 2012-09-08 04:58:43 +00:00
Benjamin Kramer
2c1f1b0513 PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for registers. 
gas accepts this and it seems to be common enough to be worth supporting. This
doesn't affect the parsing of reg operands outside of .cfi directives.

llvm-svn: 163390
 2012-09-07 14:51:35 +00:00
Manman Ren
b9d2a6fa2e Release build: guard dump functions with "ifndef NDEBUG" 
No functional change.

llvm-svn: 163339
 2012-09-06 19:06:06 +00:00
Elena Demikhovsky
9339eef307 AVX2 optimization. 
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible.

llvm-svn: 163312
 2012-09-06 12:42:01 +00:00
Michael Liao
290d2703fe Remove duplicated helper function 
llvm-svn: 163295
 2012-09-06 07:11:22 +00:00
Craig Topper
0b9e2dd7a7 Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. 
llvm-svn: 163293
 2012-09-06 06:09:01 +00:00
Craig Topper
b2bad42f00 Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. 
llvm-svn: 163292
 2012-09-06 05:15:01 +00:00
Roman Divacky
85348270cd Stop casting away const qualifier needlessly. 
llvm-svn: 163258
 2012-09-05 22:26:57 +00:00
Roman Divacky
4be967f49b Use const properly so that we dont remove const qualifier from region and MII 
by casting. Found with gcc48.

llvm-svn: 163247
 2012-09-05 21:17:34 +00:00
Craig Topper
864ef1eec5 Remove some of the patterns added in r163196. Increasing the complexity on insert_subvector into undef accomplishes the same thing. 
llvm-svn: 163198
 2012-09-05 07:26:35 +00:00
Craig Topper
f029cfe913 Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. 
llvm-svn: 163196
 2012-09-05 06:58:39 +00:00
Craig Topper
6274d26545 Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. 
llvm-svn: 163192
 2012-09-05 05:48:09 +00:00