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455 Commits

Author SHA1 Message Date
Zoran Jovanovic
d72dae73a8 [mips][microMIPS] Implement SWP and LWP instructions 
Differential Revision: http://reviews.llvm.org/D5667

llvm-svn: 224338
 2014-12-16 14:59:10 +00:00
Vladimir Medic
7915fd41c4 The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. 
llvm-svn: 223006
 2014-12-01 11:12:04 +00:00
Jozef Kolek
e3a600e129 [mips][microMIPS] Implement NOP aliases 
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440

llvm-svn: 222953
 2014-11-29 13:29:24 +00:00
Zoran Jovanovic
15712f82b0 [mips][microMIPS] Implement SWM16 and LWM16 instructions 
Differential Revision: http://reviews.llvm.org/D5579

llvm-svn: 222901
 2014-11-27 18:28:59 +00:00
Jozef Kolek
c85a4a5656 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions 
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048

llvm-svn: 222900
 2014-11-27 18:18:42 +00:00
Daniel Sanders
d7d5d4cdb1 [mips] Add synci instruction. 
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421

llvm-svn: 222899
 2014-11-27 17:28:10 +00:00
Jozef Kolek
ecfa20e7f7 [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 
Differential Revision: http://reviews.llvm.org/D6405

llvm-svn: 222847
 2014-11-26 18:56:38 +00:00
Jozef Kolek
a4e87d7a74 [mips][microMIPS] Fix JRADDIUSP instruction 
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365

llvm-svn: 222658
 2014-11-24 16:14:10 +00:00
Jozef Kolek
dd0dbf282b [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions 
Differential Revision: http://reviews.llvm.org/D5122

llvm-svn: 222653
 2014-11-24 14:39:13 +00:00
Zoran Jovanovic
ebf19d975c [mips][micromips] Implement SWM32 and LWM32 instructions 
Differential Revision: http://reviews.llvm.org/D5519

llvm-svn: 222367
 2014-11-19 16:44:02 +00:00
Jozef Kolek
2b6a42be6d [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions. 
Differential Revision: http://reviews.llvm.org/D6169

llvm-svn: 222355
 2014-11-19 13:37:51 +00:00
Jozef Kolek
0de52b5b97 [mips][microMIPS] Implement LWXS instruction. 
Differential Revision: http://reviews.llvm.org/D5407

llvm-svn: 222348
 2014-11-19 11:39:12 +00:00
Jozef Kolek
e466cd5b54 [mips][microMIPS] Implement SDBBP and RDHWR instructions. 
Differential Revision: http://reviews.llvm.org/D5240

llvm-svn: 222347
 2014-11-19 11:25:50 +00:00
Vasileios Kalintiris
9d62a870f7 [mips] Add hardware register name "hwr_ulr" ($29) 
The canonical name when printing assembly is still $29. The reason is that
GAS does not accept "$hwr_ulr" at the moment.

This addresses the comments from r221307, which reverted the original
commit r221299.

llvm-svn: 221685
 2014-11-11 11:22:39 +00:00
Vasileios Kalintiris
88cc5e39d4 Recommit "[mips] Add names and tests for the hardware registers" 
The original commit r221299 was reverted in r221307.  I removed the name
"hrw_ulr" ($29) from the original commit because two tests were failing.

llvm-svn: 221681
 2014-11-11 10:31:31 +00:00
David Majnemer
2465460895 llvm-objdump: Skip empty sections when dumping contents 
Empty sections are just noise when using objdump.
This is similar to what binutils does.

llvm-svn: 221680
 2014-11-11 09:58:25 +00:00
Toma Tabacu
5d123a7fbb [mips] Improve error/warning messages and testing for the .cpload assembler directive. 
Summary:
Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled.
Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5465

llvm-svn: 221447
 2014-11-06 10:02:45 +00:00
Zoran Jovanovic
3aa8010f59 [mips][microMIPS] Implement ANDI16 instruction 
llvm-svn: 221367
 2014-11-05 17:31:00 +00:00
Zoran Jovanovic
cc26c757fc [mips][microMIPS] Mark symbols as microMIPS if necessary 
Differential Revision: http://reviews.llvm.org/D6039

llvm-svn: 221355
 2014-11-05 16:35:20 +00:00
Zoran Jovanovic
9298c57c2a Reverted revisions 221351, 221352 and 221353. 
llvm-svn: 221354
 2014-11-05 16:19:59 +00:00
Zoran Jovanovic
d61600192c [mips][microMIPS] Implement ANDI16 instruction 
Differential Revision: http://reviews.llvm.org/D5163

llvm-svn: 221351
 2014-11-05 15:39:41 +00:00
Rafael Espindola
9c149d6662 Revert "[mips] Add names and tests for the hardware registers" 
This reverts commit r221299.

The tests

    LLVM :: MC/Disassembler/Mips/mips32.txt
    LLVM :: MC/Disassembler/Mips/mips32_le.txt

were failing.

llvm-svn: 221307
 2014-11-04 22:15:05 +00:00
Vasileios Kalintiris
2d9f60f771 [mips] Add names and tests for the hardware registers 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5763

llvm-svn: 221299
 2014-11-04 21:30:44 +00:00
Toma Tabacu
93fe1e2fb1 [mips] Improve support for the .set mips16/nomips16 assembler directives. 
Summary:
Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted).

These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled).

Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5462

llvm-svn: 221277
 2014-11-04 17:18:07 +00:00
Zoran Jovanovic
417b0378da [mips][microMIPS] Implement ADDIUR1SP instruction 
Differential Revision: http://reviews.llvm.org/D5153

llvm-svn: 220477
 2014-10-23 11:13:59 +00:00
Zoran Jovanovic
7d4ae91afe ps][microMIPS] Implement ADDIUR2 instruction 
Differential Revision: http://reviews.llvm.org/D5151

llvm-svn: 220476
 2014-10-23 11:06:34 +00:00
Zoran Jovanovic
c644ce2e43 ps][microMIPS] Implement LI16 instruction 
Differential Revision: http://reviews.llvm.org/D5149

llvm-svn: 220475
 2014-10-23 10:59:24 +00:00
Zoran Jovanovic
0172553d1e [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D5774

llvm-svn: 220474
 2014-10-23 10:42:01 +00:00
Derek Schuff
0ee9a3b81d Fix Mips nacl-mask test for new bundle-aligned label behavior 
After r220439 the behavior of labels in bundle-align mode changed,
and I neglected to update this test.

llvm-svn: 220447
 2014-10-22 23:32:00 +00:00
Zoran Jovanovic
5e356e74e3 [mips][microMIPS] Implement ADDU16 and SUBU16 instructions 
Differential Revision: http://reviews.llvm.org/D5118

llvm-svn: 220276
 2014-10-21 08:44:58 +00:00
Zoran Jovanovic
26b6fdd712 [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D5117

llvm-svn: 220275
 2014-10-21 08:32:40 +00:00
Vasileios Kalintiris
86aabae168 [mips] Add support for COP1's Branch-On-Cond-Likely instructions 
Summary: Depends on D5782

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5802

llvm-svn: 220042
 2014-10-17 14:08:28 +00:00
Vasileios Kalintiris
f0e37a4687 [mips] Add support for COP0's Branch-On-Cond-Likely instructions 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5782

llvm-svn: 220036
 2014-10-17 12:38:35 +00:00
Vasileios Kalintiris
8d39330886 [mips] Marked the DI/EI instruction aliases as MIPS32r2 
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5751

llvm-svn: 219927
 2014-10-16 15:23:52 +00:00
Zoran Jovanovic
d8488142ad [mips][microMIPS] Implement ADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5084

llvm-svn: 219500
 2014-10-10 14:37:30 +00:00
Zoran Jovanovic
437a433c43 [mips][microMIPS] Implement JR16 instruction 
Differential Revision: http://reviews.llvm.org/D5062

llvm-svn: 219498
 2014-10-10 14:02:44 +00:00
Zoran Jovanovic
454a101d3d [mips][microMIPS] Implement ADDIUS5 instruction 
Differential Revision: http://reviews.llvm.org/D5049

llvm-svn: 219495
 2014-10-10 13:45:34 +00:00
Zoran Jovanovic
d436e06cb4 ps][microMIPS] Implement JRC instruction 
Differential Revision: http://reviews.llvm.org/D5045

llvm-svn: 219494
 2014-10-10 13:31:18 +00:00
Zoran Jovanovic
b5ed47d1e5 [mips][microMIPS] Implement JALRS16 instruction 
Differential Revision: http://reviews.llvm.org/D5027

llvm-svn: 219493
 2014-10-10 13:22:28 +00:00
Daniel Sanders
208d0fa4ef [mips] Print warning when using register names not available in N32/64 
Summary:
The register names t4-t7 are not available in the N32 and N64 ABIs.
This patch prints a warning, when those names are used in N32/64,
along with a fix-it with the correct register names.

Patch by Vasileios Kalintiris

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5272

llvm-svn: 218989
 2014-10-03 15:37:37 +00:00
Joerg Sonnenberger
ba894344cc Support padding unaligned data in .text. 
llvm-svn: 218870
 2014-10-02 13:41:42 +00:00
Toma Tabacu
c4a433d332 [mips] Add assembler support for the .set nodsp directive. 
Summary: This directive is used to tell the assembler to reject DSP-specific instructions.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5142

llvm-svn: 217946
 2014-09-17 09:01:54 +00:00
Toma Tabacu
66d0e3b536 [mips] Improve the error messages given by MipsAsmParser. 
Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5065

llvm-svn: 217873
 2014-09-16 15:00:52 +00:00
Toma Tabacu
3566191dcd [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5244

llvm-svn: 217868
 2014-09-16 10:19:03 +00:00
Toma Tabacu
67271ad290 [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5242

llvm-svn: 217867
 2014-09-16 09:26:09 +00:00
Toma Tabacu
a227ffeb8e [mips] Marked the DADDiu instruction aliases as MIPS III. 
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5239

llvm-svn: 217770
 2014-09-15 14:47:46 +00:00
Zoran Jovanovic
f1edd29dad [mips][microMIPS] Implement JRADDIUSP instruction 
Differential Revision: http://reviews.llvm.org/D5046

llvm-svn: 217681
 2014-09-12 14:29:54 +00:00
Zoran Jovanovic
e18ff10a80 [mips][microMIPS] Implement BGEZALS and BLTZALS instructions 
Differential Revision: http://reviews.llvm.org/D5004

llvm-svn: 217678
 2014-09-12 13:51:58 +00:00
Zoran Jovanovic
29a4b03447 [mips][microMIPS] Implement JALS and JALRS instructions. 
Differential Revision: http://reviews.llvm.org/D5003

llvm-svn: 217676
 2014-09-12 13:43:41 +00:00
Zoran Jovanovic
4d73b21714 [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D5211

llvm-svn: 217675
 2014-09-12 13:33:33 +00:00