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123 Commits

Author SHA1 Message Date
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Evan Cheng
ff81990e49 Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. 
llvm-svn: 77967
 2009-08-03 08:41:59 +00:00
Evan Cheng
27ee95d344 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
llvm-svn: 77939
 2009-08-03 02:38:06 +00:00
Evan Cheng
3c2d9a0698 Test both darwin and linux. 
llvm-svn: 77852
 2009-08-02 02:54:34 +00:00
Eli Friedman
cd4d9ff7fa Hack to make this test work on platforms which aren't Macs. Fixing this 
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.

llvm-svn: 77785
 2009-08-01 16:37:18 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
 2009-07-31 18:35:56 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af Cleanup and include code selection for some frame index cases. 
llvm-svn: 77622
 2009-07-30 18:56:48 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng
bddff8fbe0 Remove a duplicated test. 
llvm-svn: 77020
 2009-07-25 00:24:40 +00:00
Evan Cheng
b8b61017e8 Fix these tests. 
llvm-svn: 77006
 2009-07-24 22:42:22 +00:00
Evan Cheng
bbac2397c5 Convert a test to FileCheck. 
llvm-svn: 76954
 2009-07-24 06:01:46 +00:00
Evan Cheng
90f66e1c4e Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng
f6b88eae82 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
 2009-07-23 18:27:47 +00:00
Evan Cheng
192fc19379 Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Evan Cheng
949c2404a2 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
David Goodwin
88f38c0380 Fix detection of valid BFC immediates. 
llvm-svn: 75576
 2009-07-14 00:57:56 +00:00
Evan Cheng
20086680b0 Don't put IT instruction before conditional branches. 
llvm-svn: 75361
 2009-07-11 07:26:20 +00:00
Chris Lattner
2bdd9c7807 convert test to use FileCheck, which is much more precise and faster than 
the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)

llvm-svn: 75261
 2009-07-10 18:34:47 +00:00
Evan Cheng
24f2aefc87 Add a thumb2 pass to insert IT blocks. 
llvm-svn: 75218
 2009-07-10 01:54:42 +00:00
David Goodwin
49fbd8d6b7 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
David Goodwin
d19a9aa207 Add rev16 test... xfail for now 
llvm-svn: 75012
 2009-07-08 16:15:06 +00:00
David Goodwin
5bdef4b3f7 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00
Evan Cheng
393e38e44b Add Thumb2 movcc instructions. 
llvm-svn: 74946
 2009-07-07 20:39:03 +00:00
Evan Cheng
fa864ab886 Add Thumb2 pkhbt / pkhtb. 
llvm-svn: 74895
 2009-07-07 05:35:52 +00:00
Evan Cheng
46b98516f6 Add some more Thumb2 multiplication instructions. 
llvm-svn: 74889
 2009-07-07 01:17:28 +00:00
Evan Cheng
f20e4fba49 Add thumb2 sign / zero extend with rotate instructions. 
llvm-svn: 74755
 2009-07-03 01:43:10 +00:00
Evan Cheng
162bd9cead Added indexed stores. 
llvm-svn: 74740
 2009-07-03 00:06:39 +00:00
Evan Cheng
fcab8e743a Sign extending pre/post indexed loads. 
llvm-svn: 74736
 2009-07-02 23:16:11 +00:00
Evan Cheng
dad6a41d14 Thumb2 pre/post indexed loads. 
llvm-svn: 74696
 2009-07-02 07:28:31 +00:00
David Goodwin
19aa5c7d51 Add PIC load and store patterns for Thumb-2. 
llvm-svn: 74577
 2009-07-01 00:01:13 +00:00
David Goodwin
5805e9aef5 Add thumb-2 store word, halfword, and byte. 
llvm-svn: 74555
 2009-06-30 22:11:34 +00:00
David Goodwin
aad223dd8a Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
Evan Cheng
2a527c3419 A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
David Goodwin
6ed9f9c9c5 Enhance tests to include shifted-register operand testing. 
llvm-svn: 74490
 2009-06-30 01:02:20 +00:00
David Goodwin
4f53387d26 Add Thumb-2 support for TEQ amd TST. 
llvm-svn: 74468
 2009-06-29 22:49:42 +00:00
David Goodwin
e7df96eedf Thumb-2 tests 
llvm-svn: 74464
 2009-06-29 22:25:22 +00:00
David Goodwin
9e1280adf3 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
llvm-svn: 74423
 2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
David Goodwin
90fc344e41 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. 
llvm-svn: 74355
 2009-06-26 23:13:13 +00:00
David Goodwin
4997a459c7 Thumb-2 tests 
llvm-svn: 74345
 2009-06-26 22:37:07 +00:00
David Goodwin
921faa64cd Thumb-2 has CLZ. 
llvm-svn: 74322
 2009-06-26 20:47:43 +00:00
David Goodwin
9da977f216 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
llvm-svn: 74321
 2009-06-26 20:45:56 +00:00
Daniel Dunbar
23337e07ce More spelling Count as count. 
llvm-svn: 74306
 2009-06-26 18:35:07 +00:00
Daniel Dunbar
fa37f8bf95 Spell Count as count. 
llvm-svn: 74298
 2009-06-26 18:21:54 +00:00
David Goodwin
4a98908300 Add Thumb-2 tests. 
llvm-svn: 74295
 2009-06-26 18:10:30 +00:00
David Goodwin
46eb5a7a2d ADC used to implement adde should use "adcs" opcode instead of "adc". 
llvm-svn: 74293
 2009-06-26 18:07:25 +00:00
David Goodwin
b2c485c6bd ORN and BIC tests. 
llvm-svn: 74289
 2009-06-26 16:20:06 +00:00
David Goodwin
877790aa5f Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288
 2009-06-26 16:10:07 +00:00
Evan Cheng
7883ae3121 Fix tests: Count -> count. 
llvm-svn: 74282
 2009-06-26 07:05:57 +00:00
Evan Cheng
da10be895c Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates. 
llvm-svn: 74276
 2009-06-26 05:59:16 +00:00
Daniel Dunbar
be7f3311ad Fix spelling of 'count' 
llvm-svn: 74249
 2009-06-26 01:33:02 +00:00
Evan Cheng
4ac765118d Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
llvm-svn: 74228
 2009-06-25 23:34:10 +00:00
David Goodwin
74414108e9 Use MVN for ~t2_so_imm immediates. 
llvm-svn: 74223
 2009-06-25 23:11:21 +00:00
Evan Cheng
0cced3daa8 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
llvm-svn: 74200
 2009-06-25 20:59:23 +00:00
Evan Cheng
e8c58ee743 Add Thumb2 pc relative add. 
llvm-svn: 74141
 2009-06-24 23:47:58 +00:00
Evan Cheng
f7814163db We should run these tests as well. 
llvm-svn: 74121
 2009-06-24 21:36:26 +00:00
Evan Cheng
b4139189b0 Move thumb and thumb2 tests into separate directories. 
llvm-svn: 74068
 2009-06-24 06:36:07 +00:00