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Commit Graph

151903 Commits

Author SHA1 Message Date
Reid Kleckner
3f9f99bb89 [CodeView] Dump BuildInfoSym and ProcSym type indices
I need to print the type index in hex so that I can match it in
FileCheck for a test I'm writing.

llvm-svn: 308107
2017-07-15 18:10:39 +00:00
Reid Kleckner
e88825c163 Fix mis-use of std::lower_bound
Binary search in C++ is such a PITA. =/

llvm-svn: 308106
2017-07-15 18:10:15 +00:00
Sanjay Patel
122bdff7b3 [InstCombine] improve (1 << x) & 1 --> zext(x == 0) folding
1. Add a one-use check to prevent increasing instruction count.
2. Generalize the pattern matching to include vector types.

llvm-svn: 308105
2017-07-15 17:26:01 +00:00
Craig Topper
cd3c9e2148 [InstCombine] Add test cases for (X & (Y | ~X)) -> (X & Y) where the not is an inverted compare. NFC
Do the same for (X | (Y & ~X)) -> (X | Y)

llvm-svn: 308104
2017-07-15 17:09:23 +00:00
Craig Topper
5c4bfe51a0 [InstCombine] Move 4 test cases from a test that didn't use FileCheck and merge them into a existing test file. NFC
llvm-svn: 308103
2017-07-15 17:09:22 +00:00
Sanjay Patel
ee49fdd1f5 [InstCombine] add tests for (1 << x) & 1 --> zext(x == 0) ; NFC
This fold hit the trifecta:
1. It was untested.
2. It oversteps (multiuse is not checked, so increases instruction count).
3. It is incomplete (doesn't work for vectors).

llvm-svn: 308102
2017-07-15 15:55:07 +00:00
Chandler Carruth
76c1a19de1 [wasm] Update two tests for r308025 which causes scheduling changes due
to the newly improved AA information.

llvm-svn: 308100
2017-07-15 15:44:36 +00:00
Sanjay Patel
48d27fcdd0 [InstCombine] allow (0 - x) & 1 --> x & 1 for vectors
llvm-svn: 308098
2017-07-15 15:29:47 +00:00
Sanjay Patel
f1721759e8 [InstCombine] remove dead code/tests; NFCI
These patterns and tests were added to InstSimplify with:
https://reviews.llvm.org/rL303004

llvm-svn: 308096
2017-07-15 15:01:33 +00:00
Chandler Carruth
34071b5594 Revert r308078 (and subsequent tweak in r308079) which introduces a test
that appears to exhibit non-determinism and is flaking on the bots
pretty consistently.

r308078: [ThinLTO] Ensure we always select the same function copy to import
r308079: Require asserts in new test that uses debug flag
llvm-svn: 308095
2017-07-15 13:50:26 +00:00
Florian Hahn
522d2634b3 [LoopInterchange] Add some optimization remarks.
Reviewers: anemet, karthikthecool, blitz.opensource

Reviewed By: anemet

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D35122

llvm-svn: 308094
2017-07-15 13:13:19 +00:00
Nuno Lopes
2f890dd021 [docs] AliasAnalysis: clarify that PartialAlias doesn't enforce
objects to start at the same address

As discussed on the ML, there's consensus that this is what the implementations
do and it seems sensible.

llvm-svn: 308090
2017-07-15 09:09:24 +00:00
Chandler Carruth
099fbc1e8e [PM/LCG] Teach the LazyCallGraph to maintain reference edges from every
function to every defined function known to LLVM as a library function.

LLVM can introduce calls to these functions either by replacing other
library calls or by recognizing patterns (such as memset_pattern or
vector math patterns) and replacing those with calls. When these library
functions are actually defined in the module, we need to have reference
edges to them initially so that we visit them during the CGSCC walk in
the right order and can effectively rebuild the call graph afterward.

This was discovered when building code with Fortify enabled as that is
a common case of both inline definitions of library calls and
simplifications of code into calling them.

This can in extreme cases of LTO-ing with libc introduce *many* more
reference edges. I discussed a bunch of different options with folks but
all of them are unsatisfying. They either make the graph operations
substantially more complex even when there are *no* defined libfuncs, or
they introduce some other complexity into the callgraph. So this patch
goes with the simplest possible solution of actual synthetic reference
edges. If this proves to be a memory problem, I'm happy to implement one
of the clever techniques to save memory here.

llvm-svn: 308088
2017-07-15 08:08:19 +00:00
Simon Atanasyan
e13ec84961 [mips] Handle the long-calls feature flags in the MIPS backend
If the `long-calls` feature flags is enabled, disable use of the `jal`
instruction. Instead of that call a function by by first loading its
address into a register, and then using the contents of that register.

Differential revision: https://reviews.llvm.org/D35168

llvm-svn: 308087
2017-07-15 07:14:25 +00:00
NAKAMURA Takumi
c0dbd017b7 SystemZCodeGen: Update libdeps. r308024 introduced LoopDataPrefetchPass.
llvm-svn: 308086
2017-07-15 06:32:12 +00:00
Yonghong Song
8e69371139 bpf: fix a compilation bug due to unused variable for release build
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 308083
2017-07-15 06:08:08 +00:00
Matt Arsenault
bd0ea56e67 AMDGPU: Return correct type during argument lowering
The type needs to be casted back to the original argument type.
Fixes an assert that for some reason is only run when
using -debug.

Includes an additional combine to avoid test regressions
from having conversions mixed with multiple Assert[SZ]ext
nodes. On subtargets where i16 is legal, this was producing an i32
register with an i16 AssertZExt, truncated to i16 with another i8
AssertZExt.

t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t3: i16 = truncate t2
t5: i16 = AssertZext t3, ValueType:ch:i8
t6: i8 = truncate t5
t7: i32 = zero_extend t6
llvm-svn: 308082
2017-07-15 05:52:59 +00:00
Dinar Temirbulatov
1f7aa2cc6e [SLPVectorizer] Add an extra parameter to tryScheduleBundle function, NFCI.
llvm-svn: 308081
2017-07-15 05:43:54 +00:00
Yonghong Song
907a002a39 bpf: generate better lowering code for certain select/setcc instructions
Currently, for code like below,
===
  inner_map = bpf_map_lookup_elem(outer_map, &port_key);
  if (!inner_map) {
    inner_map = &fallback_map;
  }
===
the compiler generates (pseudo) code like the below:
===
  I1: r1 = bpf_map_lookup_elem(outer_map, &port_key);
  I2: r2 = 0
  I3: if (r1 == r2)
  I4:   r6 = &fallback_map
  I5: ...
===

During kernel verification process, After I1, r1 holds a state
map_ptr_or_null. If I3 condition is not taken
(path [I1, I2, I3, I5]), supposedly r1 should become map_ptr.
Unfortunately, kernel does not recognize this pattern
and r1 remains map_ptr_or_null at insn I5. This will cause
verificaiton failure later on.

Kernel, however, is able to recognize pattern "if (r1 == 0)"
properly and give a map_ptr state to r1 in the above case.

LLVM here generates suboptimal code which causes kernel verification
failure. This patch fixes the issue by changing BPF insn pattern
matching and lowering to generate proper codes if the righthand
parameter of the above condition is a constant. A test case
is also added.

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 308080
2017-07-15 05:41:42 +00:00
Teresa Johnson
f7924370b7 Require asserts in new test that uses debug flag
This should fix bot failures from r308078.

llvm-svn: 308079
2017-07-15 05:27:57 +00:00
Teresa Johnson
0e5194420e [ThinLTO] Ensure we always select the same function copy to import
Summary:
Check if the first eligible callee is under the instruction threshold.
Checking this on the first eligible callee ensures that we don't end
up selecting different callees to import when we invoke this routine
with different thresholds due to reaching the callee via paths that
are shallower or hotter (when there are multiple copies, i.e. with
weak or linkonce linkage). We don't want to leave the decision of which
copy to import up to the backend.

Reviewers: mehdi_amini

Subscribers: inglorion, fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D35436

llvm-svn: 308078
2017-07-15 04:53:05 +00:00
Haicheng Wu
907a054583 [TTI] Refine the cost of EXT in getUserCost()
Now, getUserCost() only checks the src and dst types of EXT to decide it is free
or not. This change first checks the types, then calls isExtFreeImpl(), and
check if EXT can form ExtLoad at last. Currently, only AArch64 has customized
implementation of isExtFreeImpl() to check if EXT can be folded into its use.

Differential Revision: https://reviews.llvm.org/D34458

llvm-svn: 308076
2017-07-15 02:12:16 +00:00
Kostya Serebryany
1641f063c8 [libFuzzer] remove stale code
llvm-svn: 308075
2017-07-15 01:31:40 +00:00
Jakub Kuderski
89e4fa6df2 [Dominators] Fix reachable visitation and reenable a unit test
This fixes a minor bug in insertion to a reachable node that caused
DominatorTree.InsertDeleteExhaustive flakiness. The patch also adds
a new testcase for this exact failure.

llvm-svn: 308074
2017-07-15 01:27:16 +00:00
Jakub Kuderski
be68eaac03 [Dominators] Temporarily disable a flaky unit test
The DominatorTree.InsertDeleteExhaustive uses a RNG with a
constant seed to generate different sequences of updates. The test
fails on some buildbots and this patch disables it for now.

llvm-svn: 308070
2017-07-14 23:49:12 +00:00
Justin Bogner
2072bca540 [libFuzzer] Allow non-fuzzer args after -ignore_remaining_args=1
With this change, libFuzzer will ignore any arguments after a sigil
argument, but it will preserve these arguments at the end of the
command line when launching subprocesses. Using this, its possible to
handle positional and single-dash arguments to the program under test
by discarding everything up to -ignore_remaining_args=1 in
LLVMFuzzerInitialize.

llvm-svn: 308069
2017-07-14 23:33:04 +00:00
Adrian Prantl
687c38759a Add missing space to comment
llvm-svn: 308068
2017-07-14 23:23:58 +00:00
Jakub Kuderski
54ee12cb00 [Dominators] Remove an extra semicolon and add a missing include.
llvm-svn: 308065
2017-07-14 22:24:15 +00:00
Jakub Kuderski
2c985423a9 [Dominators] Implement incremental deletions
Summary:
This patch implements incremental edge deletions.

It also makes DominatorTreeBase store a pointer to the parent function. The parent function is needed to perform full rebuilts during some deletions, but it is also used to verify that inserted and deleted edges come from the same function.

Reviewers: dberlin, davide, grosser, sanjoy, brzycki

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35342

llvm-svn: 308062
2017-07-14 21:58:53 +00:00
Kostya Serebryany
69e146646b [libFuzzer] fix stats during merge
llvm-svn: 308061
2017-07-14 21:48:19 +00:00
Yi Kong
69f00572a2 [AArch64] Avoid selecting XZR inline ASM memory operand
Restricting register class to PointerRegClass for memory operands.

Also fix the PointerRegClass for AArch64 from GPR64 to GPR64sp, since
XZR cannot hold a memory pointer while SP is.

Fixes PR33134.

Differential Revision: https://reviews.llvm.org/D34999

llvm-svn: 308060
2017-07-14 21:46:16 +00:00
Geoff Berry
2bb37a1dab [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 1)
Summary:
This patch is the first step in reducing HW prefetcher instruction tag
collisions in inner loops for Falkor.  It adds a pass that annotates IR
loads with metadata to indicate that they are known to be strided loads,
and adds a target lowering hook that translates this metadata to a
target-specific MachineMemOperand flag.

A follow on change will use this MachineMemOperand flag to re-write
instructions to reduce tag collisions.

Reviewers: mcrosier, t.p.northover

Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34963

llvm-svn: 308059
2017-07-14 21:44:12 +00:00
Jakub Kuderski
9741522907 [Dominators] Add a missing include
llvm-svn: 308058
2017-07-14 21:38:15 +00:00
Davide Italiano
c081458f80 [AMDGPU] Throw away more dead code. NFCI.
llvm-svn: 308055
2017-07-14 21:20:29 +00:00
Jakub Kuderski
8c124fcc3f [Dominators] Implement incremental insertions
Summary:
This patch introduces incremental edge insertions based on the Depth Based Search algorithm.

Insertions should work for both dominators and postdominators.

Reviewers: dberlin, grosser, davide, sanjoy, brzycki

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35341

llvm-svn: 308054
2017-07-14 21:17:33 +00:00
Dimitry Andric
42e4363449 Fix mixed line terminators. NFC.
llvm-svn: 308052
2017-07-14 21:14:58 +00:00
Geoff Berry
9de6b5b6de [EarlyCSE] Handle calls with no MemorySSA info.
Summary:
When checking for memory dependencies between calls using MemorySSA,
handle cases where the calls have no MemoryAccess associated with them
because the AA analysis being used has determined that the call does not
read/write memory.

Fixes PR33756

Reviewers: dberlin, davide

Subscribers: mcrosier, llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D35317

llvm-svn: 308051
2017-07-14 20:13:21 +00:00
Haicheng Wu
fe94f47749 [JumpThreading] Add a pattern to TryToUnfoldSelectInCurrBB()
Add the following pattern to TryToUnfoldSelectInCurrBB()

bb:
   %p = phi [0, %bb1], [1, %bb2], [0, %bb3], [1, %bb4], ...
   %c = cmp %p, 0
   %s = select %c, trueval, falseval

The Select in the above pattern will be unfolded and then jump-threaded. The
current implementation does not allow CMP in the middle of PHI and Select.

Differential Revision: https://reviews.llvm.org/D34762

llvm-svn: 308050
2017-07-14 19:16:47 +00:00
Krzysztof Parzyszek
f2f4bc1138 [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFC
This breaks up pack-even and pack-odd into two separate operations.

llvm-svn: 308049
2017-07-14 19:02:32 +00:00
Davide Italiano
a969640f0e [AMDGPU] Garbage collect dead code. NFCI.
Unbreaks the build with GCC7.

llvm-svn: 308047
2017-07-14 18:47:29 +00:00
Craig Topper
191feb66c3 [TableGen][MC] Fix a few places where we didn't hide the underlying type of LaneBitmask very well.
One place compared with 32, which I've replaced with LaneBitmask::BitWidth.

The other places are shifts of a constant 1 by a lane number. But if LaneBitmask were to be a larger type than 32-bits like 64-bits, the 1 would need to be 1ULL to do a 64-bit shift. To hide this I've added a LanebitMask::getLane that hides the shift and make sures the 1 is casted to correct type first.

llvm-svn: 308042
2017-07-14 18:30:09 +00:00
Jakub Kuderski
aa78fc4f6e [Dominators] Make IsPostDominator a template parameter
Summary:
DominatorTreeBase used to have IsPostDominators (bool) member to indicate if the tree is a dominator or a postdominator tree. This made it possible to switch between the two 'modes' at runtime, but it isn't used in practice anywhere.

This patch makes IsPostDominator a template argument. This way, it is easier to switch between different algorithms at compile-time based on this argument and design external utilities around it. It also makes it impossible to incidentally assign a postdominator tree to a dominator tree (and vice versa), and to further simplify template code in GenericDominatorTreeConstruction.

Reviewers: dberlin, sanjoy, davide, grosser

Reviewed By: dberlin

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D35315

llvm-svn: 308040
2017-07-14 18:26:09 +00:00
Alfred Huang
18d2353dc7 [AMDGPU] Do not insert an instruction into worklist twice in movetovalu
In moveToVALU(), move to vector ALU is performed, all instrs in
the use chain will be visited. We do not want the same node to be
pushed to the visit worklist more than once.

Differential Revision: https://reviews.llvm.org/D34726

llvm-svn: 308039
2017-07-14 17:56:55 +00:00
Jakub Kuderski
c7b346758b [Dominators] Simplify block and node printing
Summary:
This patch adds `BlockPrinter`-- a small wrapper for printing CFG nodes and DomTree nodes to `raw_ostream`. It is meant to be only used internally, for debugging and printing errors.

Reviewers: dberlin, sanjoy, grosser, davide

Reviewed By: grosser, davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35286

llvm-svn: 308036
2017-07-14 16:56:35 +00:00
George Rimar
d3752565c9 [llvm-readobj] - Teach readobj to print DT_FILTER dynamic tag in human readable form.
Nothing special here, output format is similar to the format
used by binutils readelf and ELF Tool Chain readelf.

Differential revision: https://reviews.llvm.org/D35351

llvm-svn: 308033
2017-07-14 16:00:16 +00:00
Krzysztof Parzyszek
220ad04ad1 [Hexagon] Add intrinsics for data cache operations
This is the LLVM part, adding definitions for
  void @llvm.hexagon.Y2.dccleana(i8*)
  void @llvm.hexagon.Y2.dccleaninva(i8*)
  void @llvm.hexagon.Y2.dcinva(i8*)
  void @llvm.hexagon.Y2.dczeroa(i8*)
  void @llvm.hexagon.Y4.l2fetch(i8*, i32)
  void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.

llvm-svn: 308032
2017-07-14 15:58:48 +00:00
Sanjay Patel
64dbb81412 [InstCombine] convert bitwise (in)equality checks to logical ops (PR32401)
As discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32401

we have a backend transform to undo this:
https://reviews.llvm.org/rL299542

when it's likely that the xor version leads to better codegen, but we want 
this form in IR for better analysis and simplification potential.

llvm-svn: 308031
2017-07-14 15:09:49 +00:00
Simon Dardis
53d9af7a03 Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""
FileCheck is crashing on in the input file, so reverting again while
I investigate.

This reverts r308023.

llvm-svn: 308030
2017-07-14 15:08:05 +00:00
Sanjay Patel
d979f2d438 [InstCombine] add tests for PR32401; NFC
Also, add comments to a couple of tests that could be moved out of instcombine.

llvm-svn: 308029
2017-07-14 14:43:28 +00:00
Jonas Paulsson
b9c4e17557 [SystemZ] Minor fixing in SystemZScheduleZ196.td
Some minor corrections for the recently added instructions.

Review: Ulrich Weigand
llvm-svn: 308028
2017-07-14 14:30:46 +00:00