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Commit Graph

196942 Commits

Author SHA1 Message Date
Georgii Rymar
2852155a31 [yaml2obj] - Implement the "Offset" property for the Fill Chunk.
Similar to a regular section chunk, a Fill should have this property.
This patch implements it.

Differential revision: https://reviews.llvm.org/D80190
2020-05-20 13:38:48 +03:00
LLVM GN Syncbot
3a4cea3f74 [gn build] Port bcbd26bfe61 2020-05-20 09:58:47 +00:00
Benjamin Kramer
f7c7ec9b72 [gold-plugin] Unbreak the build after d9b9ce6c04764275a23cd0cf1856a35aae921af7 2020-05-20 11:56:06 +02:00
Florian Hahn
69f89dfbd9 [SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC).
SCEVExpander modifies the underlying function so it is more suitable in
Transforms/Utils, rather than Analysis. This allows using other
transform utils in SCEVExpander.

This patch was originally committed as b8a3c34eee06, but broke the
modules build, as LoopAccessAnalysis was using the Expander.

The code-gen part of LAA was moved to lib/Transforms recently, so this
patch can be landed again.

Reviewers: sanjoy.google, efriedma, reames

Reviewed By: sanjoy.google

Differential Revision: https://reviews.llvm.org/D71537
2020-05-20 10:53:40 +01:00
Kang Zhang
7355c9d744 [PowerPC] Enable machine verification for 3 passes
Summary:
For PowerPC, there are 3 passes has disabled the machine verification.
```
PPCTargetMachine.cpp:    addPass(&LiveVariablesID, false);
PPCTargetMachine.cpp:    addPass(createPPCEarlyReturnPass(), false);
PPCTargetMachine.cpp:  addPass(createPPCBranchSelectionPass(), false);
```
This patch is to enable machine verification for above three passes.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D79840
2020-05-20 09:40:25 +00:00
Georgii Rymar
284aaf11ee [llvm-readobj][test] - Deduplicate YAMLs in gnuhash.test and hash-table.test. NFCI.
We can use `-D` to generalize inputs. This patch does it.

Differential revision: https://reviews.llvm.org/D80199
2020-05-20 12:38:04 +03:00
Simon Pilgrim
2bfb874ac0 SLPVectorizer.h - remove unused CommandLine.h include. NFC 2020-05-20 09:58:38 +01:00
Simon Pilgrim
23ca92af1f CommandFlags.h - remove unnecessary includes. NFC.
Replace with forward declarations and move necessary includes down to source files.

Exposes an implicit dependency on TargetMachine.h in llvm-opt-fuzzer.cpp
2020-05-20 09:58:37 +01:00
Jay Foad
ac9c649836 [IR] Simplify BasicBlock::removePredecessor. NFCI.
This is the second attempt at landing this patch, after fixing the
KeepOneInputPHIs behaviour to also keep zero input PHIs.

Differential Revision: https://reviews.llvm.org/D80141
2020-05-20 09:58:21 +01:00
Ying Yi
e7f674751f Github access test: remove unnecessary whitespaces. 2020-05-20 09:53:44 +01:00
Jay Foad
06c33aee21 Revert "[IR] Simplify BasicBlock::removePredecessor. NFCI."
This reverts commit 59f49f7ee7f3397e000f7e11facb4a5605cd1cab.

It was causing buildbot failures.
2020-05-20 08:01:43 +01:00
Kang Zhang
f43e5e72d5 [NFC][PowerPC] Add 2 new cases to test livevars pass 2020-05-20 05:32:09 +00:00
Max Kazantsev
54b61be316 [Test] Add missing auto-generated checks into tests 2020-05-20 12:03:37 +07:00
Fangrui Song
c0bfc5f564 [Support][unittest] Fix HostTest.NumPhysicalCores on __i386__ after D78324 2020-05-19 21:51:14 -07:00
Stanislav Mekhanoshin
b7a6af4686 [AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization
Differential Revision: https://reviews.llvm.org/D80256
2020-05-19 21:37:14 -07:00
Matt Arsenault
b70e05f3f5 AMDGPU/GlobalISel: Fix bug in test register bank
The intent wasn't cases with illegal VGPR to SGPR copies.
2020-05-19 22:52:59 -04:00
QingShan Zhang
b8ab9c6736 [DAGCombine] Remove the getNegatibleCost to avoid the out of sync with getNegatedExpression
We have the getNegatibleCost/getNegatedExpression to evaluate the cost and negate the expression.
However, during negating the expression, the cost might change as we are changing the DAG,
and then, hit the assertion if we negated the wrong expression as the cost is not trustful anymore.

This patch is target to remove the getNegatibleCost to avoid the out of sync with getNegatedExpression,
and check the cost during negating the expression. It also reduce the duplicated code between
getNegatibleCost and getNegatedExpression. And fix the crash for the test in D76638

Reviewed By: RKSimon, spatel

Differential Revision: https://reviews.llvm.org/D77319
2020-05-20 02:12:16 +00:00
Matt Arsenault
2618da3d3b AMDGPU: Annotate functions that have stack objects
Relying on any MachineFunction state in the MachineFunctionInfo
constructor is hazardous, because the construction time is unclear and
determined by the first use. The function may be only partially
constructed, which is part of why we have many of these hacky string
attributes to track what we need for ABI lowering.

For SelectionDAG, all stack objects are created up-front before
calling convention lowering so stack objects are visible at
construction time. For GlobalISel, none of the IR function has been
visited yet and the allocas haven't been added to the MachineFrameInfo
yet. This should fix failing to set flat_scratch_init in GlobalISel
when needed.

This pass really needs to be turned into some kind of analysis, but I
haven't found a nice way use one here.
2020-05-19 18:51:00 -04:00
Cameron McInally
22b411bb74 [SVE] MOVPRFX zero merging test renaming
Differential Revision: https://reviews.llvm.org/D80244
2020-05-19 17:33:19 -05:00
Matt Arsenault
312d650dda GlobalISel: Copy correct flags to select
This was looking for a compare condition, and copying the compare
flags. I don't think this was ever correct outside of certain min/max
patterns which aren't checked, but this probably predates select
instructions having fast math flags.
2020-05-19 18:31:24 -04:00
Matt Arsenault
10dc424440 AMDGPU: Fix DAG divergence for implicit function arguments
This should be directly implied from the register class, and there's
no need to special case live ins here. This was getting the wrong
answer for the queue ptr argument in callable functions, since it's
not an explicit IR argument and is always uniform.

Fixes not using scalar loads for the aperture in addrspacecast
lowering, and any other places that use implicit SGPR arguments.
2020-05-19 18:11:34 -04:00
Matt Arsenault
c07c3f775b AMDGPU: Use member initializers in MFI 2020-05-19 18:11:34 -04:00
Brian Cain
ededcfd109 [Hexagon] pX.new cannot be used with p3:0 as producer
Writes to p3:0 do not produce new values, we should bar any .new
consumer trying to use it as a producer.
2020-05-19 17:06:34 -05:00
Matt Arsenault
d57c9ccec0 GlobalISel: Remove unused include 2020-05-19 17:56:55 -04:00
Matt Arsenault
158066083b CodeGen: Use Register 2020-05-19 17:56:55 -04:00
Nico Weber
f292439160 [gn build] Try harder to unbreak Windows build after f8e833a501. 2020-05-19 17:14:08 -04:00
Eli Friedman
71387bfac5 [AArch64] Disable MachineOutliner on Windows.
The handling of unwind info is broken, so disable it for now.
2020-05-19 13:49:03 -07:00
Benjamin Kramer
48794a1de1 Give helpers internal linkage. NFC. 2020-05-19 22:16:37 +02:00
Nico Weber
9846f00871 [gn build] Try to unbreak Windows build after f8e833a501. 2020-05-19 16:14:04 -04:00
Sébastien Marchand
5acc4e3b48 [gn build] Add a flag zlib_path to provide the path to zlib on Windows.
Also, automatically set llvm_enable_zlib to true when zlib_path is set.

Differential Revision: https://reviews.llvm.org/D80042
2020-05-19 16:00:54 -04:00
Lei Huang
ed4f8a73ef [PowerPC][NFC] Cleanup load/store spilling code
Summary: Cleanup and commonize code used for spilling to the stack.

Reviewers: stefanp, nemanjai, #powerpc, kamaub

Reviewed By: nemanjai, #powerpc, kamaub

Subscribers: kamaub, hiraditya, wuzish, shchenz, llvm-commits, kbarton

Tags: #llvm, #powerpc

Differential Revision: https://reviews.llvm.org/D79736
2020-05-19 14:57:32 -05:00
Sanjay Patel
a6e0c3bcd6 [PGOProfile] make test less brittle; NFC
This test may fail just from cosmetic diffs because the values change names.
This is a minimal diff to work-around that, but more may be needed.
2020-05-19 15:56:29 -04:00
Thomas Lively
ee4c671218 [WebAssembly] Fix bug in custom shuffle combine
Summary:
The code previously assumed the source of the bitcast in the combined
pattern was a vector type, but this is not always true. This patch
adds a check to avoid an assertion failure in that case.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80164
2020-05-19 12:54:15 -07:00
Thomas Lively
b0e2caa549 [WebAssembly] Implement i64x2.mul and remove i8x16.mul
Summary:
This reflects changes in the spec proposal made since basic arithmetic
was first implemented.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D80174
2020-05-19 12:50:44 -07:00
Zola Bridges
30f7774b9b [llvm][docs] Add step by step git to GettingStarted
Summary:
Due to deleting the git llvm script, folks were asking for better documentation
about how to use git in order to commit to the Github repo. I added some step
by step git commands to make the usage clearer.

Context link: http://lists.llvm.org/pipermail/llvm-dev/2020-May/141640.html

Reviewed By: spatel, mehdi_amini

Differential Revision: https://reviews.llvm.org/D80088
2020-05-19 12:14:17 -07:00
Sanjay Patel
95ded6137f [PhaseOrdering] add tests for x86 horizontal math ops (PR41813); NFC 2020-05-19 14:54:19 -04:00
Sanjay Patel
e03319223b [PhaseOrdering] make different pass manager runs equivalent; NFC
I don't see any difference from the 'avx' setting, so leaving that
off until there's a need for it.
2020-05-19 14:52:57 -04:00
Jay Foad
e01d2d79a8 [IR] Simplify BasicBlock::removePredecessor. NFCI.
Differential Revision: https://reviews.llvm.org/D80141
2020-05-19 19:34:49 +01:00
Christopher Tetreault
16b41633e9 [SVE] Add specialized getters to derived vector types
Summary:
Add versions of the specialized getters in base VectorType to the
derived vector types that return derived pointers. This reduces the
amount of casting you need to do when working with derived vectors

Reviewers: efriedma, david-arm, fpetrogalli, craig.topper

Reviewed By: david-arm

Subscribers: tschuett, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80026
2020-05-19 11:27:18 -07:00
Nikita Popov
194d144faa [LVI] Don't require DominatorTree in LVI (NFC)
After D76797 the dominator tree is no longer used in LVI, so we
can remove it as a pass dependency, and also get rid of the
dominator tree enabling/disabling logic in JumpThreading.

Apart from cleaning up the code, this also clarifies LVI
cache consistency, in that the LVI cache can no longer
depend on whether the DT was or wasn't enabled due to
pending DT updates at any given time.

Differential Revision: https://reviews.llvm.org/D76985
2020-05-19 20:21:46 +02:00
Craig Topper
afc2906e83 [StackColoring] When remapping alloca's move the To alloca if the From alloca is before it.
If To is after From its possible that there's a use of From
between them.

Fixes issue reported here http://lists.llvm.org/pipermail/llvm-dev/2020-May/141421.html

Differential Revision: https://reviews.llvm.org/D80101
2020-05-19 10:37:27 -07:00
Andrea Di Biagio
3be35c731b [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC
This effectively splits the scheduling WriteVecMaskedStore(Y) classes
into four different classes (one per each variant).

The new VecMaskedStore scheduling classes are now correctly marked as
'unsupported' by the bdver2 and btver2 models.

No functional change intended.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D80201
2020-05-19 17:35:10 +01:00
Florian Hahn
8f2546abf8 [LV] Remove duplicated return stmt (NFC). 2020-05-19 17:20:50 +01:00
Jay Foad
ed678c9f29 [InstCombine] Remove hasNoInfs check for pow(C,y) -> exp2(log2(C)*y)
We already check hasNoNaNs and that x is finite and strictly positive.
That only leaves the following special cases (taken from the Linux man
page for pow):

If x is +1, the result is 1.0 (even if y is a NaN).
If the absolute value of x is less than 1, and y is negative infinity, the result is positive infinity.
If the absolute value of x is greater than 1, and y is negative infinity, the result is +0.
If the absolute value of x is less than 1, and y is positive infinity, the result is +0.
If the absolute value of x is greater than 1, and y is positive infinity, the result is positive infinity.

The first case is handled elsewhere, and this transformation preserves
all the others, so there is no need to limit it to hasNoInfs.

Differential Revision: https://reviews.llvm.org/D79409
2020-05-19 17:06:05 +01:00
Florian Hahn
4dad997477 [VPlan] Fix comment for User in VPWidenSelectRecipe (NFC).
The comment was referring the arguments of the call, but the recipe
widens a select.
2020-05-19 15:31:39 +01:00
Simon Pilgrim
25907bc843 MCTargetOptionsCommandFlags.h - remove unnecessary includes. NFC.
Replace with MCTargetOptions forward declaration and move includes down to MCTargetOptionsCommandFlags.cpp
2020-05-19 15:15:26 +01:00
Simon Pilgrim
fd2f73cdf8 CommandLine.h - remove unnecessary raw_ostream forward declaration. NFC.
We already have to include raw_ostream.h.
2020-05-19 15:15:25 +01:00
Simon Pilgrim
f3e4ea054e MachineBasicBlock.h - remove unnecessary includes. NFC.
Don't explicitly include ilist_node.h + simple_ilist.h - we already include ilist.h that include these for us and all references are in terms of that.

The rest can be covered by forward declarations.
2020-05-19 15:15:25 +01:00
Florian Hahn
24707c2618 [VPlan] Add & use VPValue operands for VPReplicateRecipe (NFC).
This patch adds VPValue version of the instruction operands to
VPReplicateRecipe and uses them during code-generation.

Reviewers: Ayal, gilr, rengolin

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D80114
2020-05-19 15:12:17 +01:00
Florian Hahn
96e6121c8e [VPlan] Remove unique_ptr from VPBranchOnRecipeMask (NFC).
We can remove a dynamic memory allocation, by checking the number of
operands: no operands = all true, 1 operand = mask.

Reviewers: Ayal, gilr, rengolin

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D80110
2020-05-19 15:01:37 +01:00