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Author SHA1 Message Date
Chris Lattner
2a30ed887c new testcase 
llvm-svn: 23316
 2005-09-12 17:08:15 +00:00
Chris Lattner
ab0448905e Add a new getLoopLatch() method. 
llvm-svn: 23315
 2005-09-12 17:03:55 +00:00
Chris Lattner
f3471861a6 new method 
llvm-svn: 23314
 2005-09-12 17:03:16 +00:00
Chris Lattner
780ffd9c1f _test: 
li r2, 0
LBB_test_1:     ; no_exit.2
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmpwi cr0, r2, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r2, 1
        stw r2, 0(r4)
        blr
[zion ~/llvm]$ cat > ~/xx
Uses of IV's outside of the loop should use hte post-incremented version
of the IV, not the preincremented version.  This helps many loops (e.g. in sixtrack)
which used to generate code like this (this is the code from the
dont-hoist-simple-loop-constants.ll testcase):

_test:
        li r2, 0                 **** IV starts at 0
LBB_test_1:     ; no_exit.2
        or r5, r2, r2            **** Copy for loop exit
        li r2, 0
        stw r2, 0(r3)
        addi r3, r3, 4
        addi r2, r5, 1
        addi r6, r5, 2           **** IV+2
        cmpwi cr0, r6, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r5, 2       ****  IV+2
        stw r2, 0(r4)
        blr

And now generated code like this:

_test:
        li r2, 1               *** IV starts at 1
LBB_test_1:     ; no_exit.2
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmpwi cr0, r2, 701     *** IV.postinc + 0
        blt cr0, LBB_test_1
LBB_test_2:     ; loopexit.2.loopexit
        stw r2, 0(r4)          *** IV.postinc + 0
        blr

llvm-svn: 23313
 2005-09-12 06:04:47 +00:00
Chris Lattner
963c549bc9 new testcase 
llvm-svn: 23312
 2005-09-12 05:50:15 +00:00
Chris Lattner
773456a944 Regenerate 
llvm-svn: 23311
 2005-09-12 05:30:06 +00:00
Chris Lattner
8b34f3d20d Rearrange two rules, which apparently makes some versions of bison happier. 
llvm-svn: 23310
 2005-09-12 05:29:43 +00:00
Chris Lattner
94198e530b Make sure to disable 64-bit extensions for this test 
llvm-svn: 23309
 2005-09-11 03:50:38 +00:00
Jeff Cohen
ce2b74a2b5 Fix more Visual Studio build problems. 
llvm-svn: 23308
 2005-09-10 02:33:17 +00:00
Jeff Cohen
7e6b5c60fc Fix miscellaneous Visual Studio build problems. 
llvm-svn: 23307
 2005-09-10 02:00:02 +00:00
Chris Lattner
ddec75fdf6 implement Transforms/LoopStrengthReduce/dont-hoist-simple-loop-constants.ll. 
We used to emit this code for it:

_test:
        li r2, 1     ;; Value tying up a register for the whole loop
        li r5, 0
LBB_test_1:     ; no_exit.2
        or r6, r5, r5
        li r5, 0
        stw r5, 0(r3)
        addi r5, r6, 1
        addi r3, r3, 4
        add r7, r2, r5  ;; should be addi r7, r5, 1
        cmpwi cr0, r7, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r6, 2
        stw r2, 0(r4)
        blr

now we emit this:

_test:
        li r2, 0
LBB_test_1:     ; no_exit.2
        or r5, r2, r2
        li r2, 0
        stw r2, 0(r3)
        addi r3, r3, 4
        addi r2, r5, 1
        addi r6, r5, 2   ;; whoa, fold those adds!
        cmpwi cr0, r6, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r5, 2
        stw r2, 0(r4)
        blr

more improvement coming.

llvm-svn: 23306
 2005-09-10 01:18:45 +00:00
Chris Lattner
97f62d0f5e new testcase 
llvm-svn: 23305
 2005-09-10 01:14:37 +00:00
Chris Lattner
00e9278551 PowerPC cannot truncstore i1 natively 
llvm-svn: 23304
 2005-09-10 00:21:06 +00:00
Chris Lattner
38fb15db44 Allow targets to say they don't support truncstore i1 (which includes a mask 
when storing to an 8-bit memory location), as most don't.

llvm-svn: 23303
 2005-09-10 00:20:18 +00:00
Chris Lattner
52a8cb35e6 Add a missing #include, patch courtesy of Baptiste Lepilleur. 
llvm-svn: 23302
 2005-09-09 23:53:39 +00:00
Chris Lattner
cae9229d6e Fix a problem duraid encountered on itanium where this folding: 
select (x < y), 1, 0 -> (x < y) incorrectly: the setcc returns i1 but the
select returned i32.  Add the zero extend as needed.

llvm-svn: 23301
 2005-09-09 23:00:07 +00:00
Chris Lattner
85884e9b8a Fix a crash viewing dags that have target nodes in them 
llvm-svn: 23300
 2005-09-09 22:35:03 +00:00
Chris Lattner
ad8728e9a6 I forgot that we always spill fp values as 64-bits. Implement spill folding 
for FP as well.  This triggers a couple dozen times on 177.mesa (for example).

llvm-svn: 23299
 2005-09-09 21:59:44 +00:00
Chris Lattner
da77012825 Fix a problem that Nate noticed, where spill code was not getting coallesced 
with copies, leading to code like this:

       lwz r4, 380(r1)
       or r10, r4, r4    ;; Last use of r4

By teaching the PPC backend how to fold spills into copies, we now get this
code:

       lwz r10, 380(r1)

wow. :)

This reduces a testcase nate sent me from 1505 instructions to 1484.

Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch

llvm-svn: 23298
 2005-09-09 21:46:49 +00:00
Chris Lattner
c3959855af code cleanup 
llvm-svn: 23297
 2005-09-09 20:51:08 +00:00
Chris Lattner
e7610bc599 Use continue in the use-processing loop to make it clear what the early exits 
are, simplify logic, and cause things to not be nested as deeply.  This also
uses MRI->areAliases instead of an explicit loop.

No functionality change, just code cleanup.

llvm-svn: 23296
 2005-09-09 20:29:51 +00:00
Nate Begeman
8422b3637e Last round of 2-node folds from SD.cpp. Will move on to 3 node ops such 
as setcc and select next.

llvm-svn: 23295
 2005-09-09 19:49:52 +00:00
Chris Lattner
fc17fe0e6d remove debugging code *slaps head* 
llvm-svn: 23294
 2005-09-09 19:19:20 +00:00
Chris Lattner
8d8506f8e2 When spilling a live range that is used multiple times by one instruction, 
only add a reload live range once for the instruction.  This is one step
towards fixing a regalloc pessimization that Nate notice, but is later undone
by the spiller (so no code is changed).

llvm-svn: 23293
 2005-09-09 19:17:47 +00:00
Chris Lattner
8d654c32cb Teach the code generator that rlwimi is commutable if the rotate amount 
is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292
 2005-09-09 18:17:41 +00:00
Jim Laskey
e92c64bfe7 Added targets to speed up build of llc. 
llvm-svn: 23291
 2005-09-09 17:50:20 +00:00
Chris Lattner
491dda08c5 New testcase, neither should require a register-register copy 
llvm-svn: 23290
 2005-09-09 17:48:57 +00:00
Chris Lattner
ada7ac14a1 add an accessor to provide more checking 
llvm-svn: 23289
 2005-09-09 01:15:01 +00:00
Chris Lattner
2490f8f606 use new accessors to simplify code. Add checking to make sure top-level instr 
definitions are void

llvm-svn: 23288
 2005-09-09 01:11:44 +00:00
Chris Lattner
2b656c6102 add some accessors 
llvm-svn: 23287
 2005-09-09 01:11:17 +00:00
Chris Lattner
e8cc191dd6 Introduce two new concepts: 
1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.

llvm-svn: 23286
 2005-09-09 00:39:56 +00:00
Chris Lattner
334e21eb98 Fix incorrect comment 
llvm-svn: 23285
 2005-09-08 23:26:30 +00:00
Chris Lattner
a6d21c974c Implement a complete type inference system for dag patterns, based on the 
constraints defined in the DAG node definitions in the .td files.  This
allows us to infer (and check!) the types for all nodes in the current
ppc .td file.  For example, instead of:

Inst pattern EQV:       (set GPRC:i32:$rT, (xor (xor GPRC:i32:$rA, GPRC:i32:$rB), (imm)<<Predicate_immAllOnes>>))

we now fully infer:

Inst pattern EQV:       (set:void GPRC:i32:$rT, (xor:i32 (xor:i32 GPRC:i32:$rA, GPRC:i32:$rB), (imm:i32)<<Predicate_immAllOnes>>))

from:  (set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))
llvm-svn: 23284
 2005-09-08 23:22:48 +00:00
Chris Lattner
a3a924efdd whitespace/comment changes, no functionality diffs 
llvm-svn: 23283
 2005-09-08 23:17:26 +00:00
Chris Lattner
e2fb8f3a77 Compute the value types that are natively supported by a target. 
llvm-svn: 23282
 2005-09-08 21:43:21 +00:00
Chris Lattner
152a72de2c Parse information about type constraints on SDNodes 
llvm-svn: 23281
 2005-09-08 21:27:15 +00:00
Chris Lattner
ef07fffe37 use node info in the one place we currently use it 
llvm-svn: 23280
 2005-09-08 21:04:46 +00:00
Chris Lattner
d9930002aa start parsing SDNode info records 
llvm-svn: 23279
 2005-09-08 21:03:01 +00:00
Nate Begeman
1675c67c62 Move yet more folds over to the dag combiner from sd.cpp 
llvm-svn: 23278
 2005-09-08 20:18:10 +00:00
Chris Lattner
ca093b4f92 Add a bunch of stuff needed for node type inference. Move 'BLR' down with 
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts

llvm-svn: 23277
 2005-09-08 19:50:41 +00:00
Chris Lattner
515c19f56d Fix indentation 
llvm-svn: 23276
 2005-09-08 19:47:28 +00:00
Chris Lattner
b07d2cc2eb regenerate 
llvm-svn: 23275
 2005-09-08 18:48:47 +00:00
Chris Lattner
df9876cdb7 Add support for automatically created anonymous definitions. 
This implements Regression/TableGen/AnonDefinitionOnDemand.td

llvm-svn: 23274
 2005-09-08 18:48:23 +00:00
Chris Lattner
f315628427 x and X should be structurally identical 
llvm-svn: 23273
 2005-09-08 18:47:43 +00:00
Chris Lattner
08274846d1 new expression type 
llvm-svn: 23272
 2005-09-08 18:47:21 +00:00
Chris Lattner
9e7e8d43e8 regenerate 
llvm-svn: 23271
 2005-09-08 18:22:57 +00:00
Chris Lattner
2e3ed074d8 Tabs to spaces. 
llvm-svn: 23270
 2005-09-08 18:22:35 +00:00
Chris Lattner
03637c7200 Keep names even when inlining. This allows us to realize that ADDI is: 
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>:$imm))

not:

(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>))

(we keep the ":$imm")

llvm-svn: 23269
 2005-09-08 17:45:12 +00:00
Chris Lattner
7d0a6e4db4 add patterns for x?oris? 
llvm-svn: 23268
 2005-09-08 17:40:49 +00:00
Chris Lattner
c23c950d73 add patterns to the addi/addis/mulli etc instructions. Define predicates 
for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267
 2005-09-08 17:33:10 +00:00