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Commit Graph

4739 Commits

Author SHA1 Message Date
Jim Grosbach
2ab898973a ARM MCRR/MCRR2 immediate operand range checking.
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831 ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Evan Cheng
24257cb9ea Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Jim Grosbach
e18641e454 Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179
2011-07-14 19:47:47 +00:00
Benjamin Kramer
8833af7c47 Don't leak operands when putting them into a shift.
llvm-svn: 135169
2011-07-14 18:41:22 +00:00
Jim Grosbach
aebb9cdf68 Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Jim Grosbach
4b63d59acb ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach
2ee8287c62 DMB instalias needs the same predicate as the instruction.
llvm-svn: 135112
2011-07-14 00:10:26 +00:00
Jim Grosbach
5a96cebd81 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach
3eb4f0de5e Update comments. These are for assembler, too.
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
Owen Anderson
c68f12ff30 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach
c9e49f3b51 Revert 135093. Think-o.
llvm-svn: 135094
2011-07-13 22:06:11 +00:00
Jim Grosbach
545a3f4802 Correct range for thumb co-processor immediate
llvm-svn: 135093
2011-07-13 22:03:11 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach
76ba2e7e9c Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
2011-07-13 21:35:10 +00:00
Jim Grosbach
385d9a3e57 Parameterize away the ARM T1Cop class.
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach
d3b15141b8 Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach
93cf7d8372 Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach
4ca79b8d2c Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach
0caa098513 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach
ab030d8a81 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach
9e021b5281 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
5c366bfb36 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach
7dbb39dffa Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
bcc9f6f31a 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach
e0fc4019f9 Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
2011-07-13 15:34:57 +00:00
Evan Cheng
ddc415a907 Add an entry.
llvm-svn: 135024
2011-07-13 01:33:00 +00:00
Evan Cheng
37ff73dfaf Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Jay Foad
cbe48cd2ac Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Bill Wendling
6bcdd65b95 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Evan Cheng
b25cb9755b Most MCCodeEmitter's don't meed MCContext.
llvm-svn: 134922
2011-07-11 21:24:15 +00:00
Jim Grosbach
fae61bb435 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach
93f2ebb5e7 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jay Foad
0ec904296e De-constify Types in StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134893
2011-07-11 09:56:20 +00:00
Evan Cheng
1346a63a0f - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Cameron Zwarich
ff18692885 Fix <rdar://problem/9751331>.
llvm-svn: 134882
2011-07-11 01:29:42 +00:00
Jakub Staszak
3e40788ce3 Use BranchProbability instead of floating points in IfConverter.
llvm-svn: 134858
2011-07-10 02:58:07 +00:00
Evan Cheng
c9e252df68 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Evan Cheng
1f0f41a820 Fix indentation.
llvm-svn: 134764
2011-07-08 22:49:55 +00:00
Evan Cheng
71dc177796 Add support for ARM / Thumb mode switching with .code 16 and .code 32.
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Jim Grosbach
dbbbb6c315 Mark tBRIND as predicable.
llvm-svn: 134758
2011-07-08 22:33:49 +00:00
Jim Grosbach
0f2da5e9fc Pseudo-ize tBRIND.
llvm-svn: 134755
2011-07-08 22:25:23 +00:00
Jim Grosbach
2b8103505a Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746
2011-07-08 21:50:04 +00:00
Cameron Zwarich
c23366d357 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
2011-07-08 21:39:21 +00:00
Jim Grosbach
63e02375a8 Pseudo-ize tBX_RET and tBX_RET_vararg.
llvm-svn: 134739
2011-07-08 21:10:35 +00:00
Benjamin Kramer
85b2770a1c Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.
Found by valgrind.

llvm-svn: 134738
2011-07-08 21:06:23 +00:00
Jim Grosbach
611219a00c Shuffle productions around a bit.
No functional change.

llvm-svn: 134737
2011-07-08 21:04:05 +00:00