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Commit Graph

154792 Commits

Author SHA1 Message Date
Sam Clegg
2aed7fe062 [WebAssembly] Allow each data segment to specify its own alignment
Also, add a flags field as we will almost certainly
be needing that soon too.

Differential Revision: https://reviews.llvm.org/D38296

llvm-svn: 314534
2017-09-29 16:50:08 +00:00
Hongbin Zheng
470b0e3bed [SimplifyIndVar] Do not fail when we constant fold an IV user to ConstantPointerNull
The type of a SCEVConstant may not match the corresponding LLVM Value.
In this case, we skip the constant folding for now.

TODO: Replace ConstantInt Zero by ConstantPointerNull
llvm-svn: 314531
2017-09-29 16:32:12 +00:00
Nicolai Haehnle
e0ed17495b AMDGPU: fix bad test exposed by r314522
The test attempts to use -1 as carry-in for v_addc_*.

Before writing r314522, I did actually test this on real hardware,
and found that it doesn't work. So r314522 is correct in restricting
the carry-in operand: just remove those tests to make things pass
again.

llvm-svn: 314530
2017-09-29 16:07:05 +00:00
Teresa Johnson
d494354a97 [ThinLTO] Use decimal suffix for promoted values to match demanglers
Summary:
Demanglers such as libiberty know how to strip suffixes of the form
\.[a-zA-Z]+\.\d+, but our current promoted value suffixes are
.llvm.${modulehash}, where the module hash is in hex. Change the
module hash to decimal to allow demanglers to handle this.

Reviewers: danielcdh

Subscribers: llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D38405

llvm-svn: 314527
2017-09-29 15:55:42 +00:00
Jonas Devlieghere
dc65054cf8 [dwarfdump][NFC] Consistent printing of address ranges
This implement the insertion operator for DWARF address ranges so they
are consistently printed as [LowPC, HighPC).

While a dump method might have felt more consistent, it is used
exclusively for printing error messages in the verifier and never used
for actual dumping. Hence this approach is more intuitive and creates
less clutter at the call sites.

Differential revision: https://reviews.llvm.org/D38395

llvm-svn: 314523
2017-09-29 15:41:22 +00:00
Nicolai Haehnle
527d1f104d AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.

Additionally, inline constants do not work. At least,

   v_addc_u32_e64 v0, vcc, v0, v1, -1

which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.

The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine

   s_mov_b64 s[0:1], exec
   v_cndmask_b32_e64 v0, v1, v2, s[0:1]

into

   v_mov_b32 v0, v3

but it's not particularly high priority.

Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*

llvm-svn: 314522
2017-09-29 15:37:31 +00:00
Jun Bum Lim
dd78ed1cc5 Use the basic cost if a GEP is not used as addressing mode
Summary:
Currently, getGEPCost() returns TCC_FREE whenever a GEP is a legal addressing mode in the target.
However, since it doesn't check its actual users, it will return FREE even in cases
where the GEP cannot be folded away as a part of actual addressing mode.
For example, if an user of the GEP is a call instruction taking the GEP as a parameter,
then the GEP may not be folded in isel.

Reviewers: hfinkel, efriedma, mcrosier, jingyue, haicheng

Reviewed By: hfinkel

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D38085

llvm-svn: 314517
2017-09-29 14:50:16 +00:00
Jonas Paulsson
46e43049cf [SystemZ] implement shouldCoalesce()
Implement shouldCoalesce() to help regalloc avoid running out of GR128
registers.

If a COPY involving a subreg of a GR128 is coalesced, the live range of the
GR128 virtual register will be extended. If this happens where there are
enough phys-reg clobbers present, regalloc will run out of registers (if
there is not a single GR128 allocatable register available).

This patch tries to allow coalescing only when it can prove that this will be
safe by checking the (local) interval in question.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D37899
https://bugs.llvm.org/show_bug.cgi?id=34610

llvm-svn: 314516
2017-09-29 14:31:39 +00:00
Simon Pilgrim
e225e27c36 Fix spelling in comments. NFCI.
llvm-svn: 314515
2017-09-29 14:13:47 +00:00
Amara Emerson
e26596654a [X86] Improve codegen for inverted overflow checking intrinsics.
Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val)

Differential Revision: https://reviews.llvm.org/D38161

llvm-svn: 314514
2017-09-29 13:53:44 +00:00
Sam Parker
5e3882c1d0 [ARM] v8.3-a complex number support
New instructions are added to AArch32 and AArch64 to aid
floating-point multiplication and addition of complex numbers, where
the complex numbers are packed in a vector register as a pair of
elements. The Imaginary part of the number is placed in the more
significant element, and the Real part of the number is placed in the
less significant element.

This patch adds assembler for the ARM target.

Differential Revision: https://reviews.llvm.org/D36789

llvm-svn: 314511
2017-09-29 13:11:33 +00:00
Michael Zuckerman
1d8a8c111e Small modification <NFC>
Change-Id: I360abccee12cae29bd2ac4f8399c9ecc92eb7f13
llvm-svn: 314510
2017-09-29 12:45:54 +00:00
Simon Pilgrim
5218ad3e92 Fix Wmismatched-tags warning.
InlineAsmIdentifierInfo was declared a class in some places and a class in others.

llvm-svn: 314508
2017-09-29 11:42:05 +00:00
Aleksandar Beserminji
0696878327 [mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Recommitting r314497. This version does not contain test which fails
when compiler is not build in debug mode.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314507
2017-09-29 11:05:02 +00:00
Aleksandar Beserminji
e374ea3b12 Revert "[mips] Reordering callseq* nodes to be linear"
Added test relies on the compiler being built in debug mode,
which may not be the case.

This reverts commit r314497.

llvm-svn: 314506
2017-09-29 10:52:03 +00:00
Simon Dardis
c09ecb8c45 [mips] Add missing license info, formatting changes. NFCI
Add missing license information to MicroMipsInstrFPU.td and
fix most of the formatting errors present. Others will be
addressed in a follow up commits.

llvm-svn: 314505
2017-09-29 10:08:06 +00:00
Simon Pilgrim
9b374a0625 [X86][SSE] Added more tests for vector multiplications as utility for D37896
Added additional tests for vector multiplications with multipliers that are:
 * powers of 2 displaced by 1,
 * product of a power of 2 displaced by one with another power of 2.

Patch by @pacxx (Michael Haidl)

Differential Revision: https://reviews.llvm.org/D38350

llvm-svn: 314504
2017-09-29 10:02:01 +00:00
Aleksandar Beserminji
b74747d3a9 [mips] Add test cases for dext/dins family of instructions
Add missing test cases for dext, dextm, dextu, dins, dinsm and
dinsu instructions.

Differential Revision: https://reviews.llvm.org/D37741

llvm-svn: 314503
2017-09-29 09:53:24 +00:00
Tim Renouf
7937cd8c35 [AMDGPU] calling conventions for AMDPAL OS type
Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502
2017-09-29 09:51:22 +00:00
Tim Renouf
9e2adaa646 [AMDGPU] AMDPAL scratch buffer support
Summary:
Added support for scratch (including spilling) for OS type amdpal:
generates code to set up the scratch descriptor if it is needed.

With amdpal, the scratch resource descriptor is loaded from offset 0 of
the global information table. The low 32 bits of the address of the
global information table is passed in s0.

Added amdgpu-git-ptr-high function attribute to hard-wire the high 32
bits of the address of the global information table. If the function
attribute is not specified, or is 0xffffffff, then the backend generates
code to use the high 32 bits of pc.

The documentation for the AMDPAL ABI will be added in a later commit.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye

Differential Revision: https://reviews.llvm.org/D37483

llvm-svn: 314501
2017-09-29 09:49:35 +00:00
Tim Renouf
fd2610a820 [Triple] Add AMDPAL operating system type
Summary:
This operating system type represents the AMDGPU PAL runtime, and will
be required by the AMDGPU backend in order to generate correct code for
this runtime.

Currently it generates the same code as not specifying an OS at all.
That will change in future commits.

Patch from Tim Corringham.

Subscribers: arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D37380

llvm-svn: 314500
2017-09-29 09:48:12 +00:00
Jonas Devlieghere
2c34a28901 [dwarfdump][NFC] Consistent errors and warnings with --verify
This patch introduces 3 helper functions: error(), warn() and note() to
make printing  during verification more consistent. When supported, the
respective prefixes are printed in color using the same color scheme as
clang.

Differential revision: https://reviews.llvm.org/D38368

llvm-svn: 314498
2017-09-29 09:33:31 +00:00
Aleksandar Beserminji
7b8a0bbb27 [mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314497
2017-09-29 09:32:14 +00:00
Coby Tayree
ebe6f5af2f [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions
Allow the proper recognition of Enum values and global variables inside ms inline-asm memory / immediate expressions, as they require some additional overhead and treated incorrect if doesn't early recognized.
supersedes D33278, D35774

Differential Revision: https://reviews.llvm.org/D37412

llvm-svn: 314493
2017-09-29 07:02:46 +00:00
Adam Nemet
7be0e0350d Make find_opt_files vararg
This is slightly less verbose for the common case of a single build directory
and more intuitive when using this API directly from the interpreter.

llvm-svn: 314491
2017-09-29 05:20:53 +00:00
Lang Hames
0d3d318d21 [ORC] Replace decltype with a concrete type to make MSVC happy.
This should fix some build failures on windows bots due to r314486.

llvm-svn: 314490
2017-09-29 05:03:43 +00:00
Brian Gesiak
b3a2f3e82d [CMake] Fix typo "Wraning" (NFC)
Summary:
The typo was added in https://reviews.llvm.org/rL247151.
It should be "warning", not "wraning".

llvm-svn: 314486
2017-09-29 02:48:07 +00:00
Saleem Abdulrasool
44300c3e52 llvm-readobj: fix a few typos (NFC)
Correct the spelling of multiple in a couple of sites.

Patch by Alex Langford!

llvm-svn: 314485
2017-09-29 02:45:44 +00:00
Sanjoy Das
bddae0ddb8 Revert "[BypassSlowDivision] Improve our handling of divisions by constants"
This reverts commit r314253.  It causes a miscompile on P100 in an internal
benchmark.  Reverting while I investigate.

llvm-svn: 314482
2017-09-29 00:54:16 +00:00
Adrian Prantl
19d0a6e426 llvm-dwarfdump: support .apple-namespaces in --find
llvm-svn: 314481
2017-09-29 00:52:33 +00:00
Marek Sokolowski
f06cd2b407 [llvm-rc] Import all make_unique invocations from llvm namespace.
Previous patch fixed one of LLVM buildbots (lld-x86_64-win7).
However, some others have already been failing because of make_unique
compilation error (llvm-clang-x86_64-expensive-checks-win).

llvm-svn: 314480
2017-09-29 00:33:57 +00:00
Adrian Prantl
d2beca911e llvm-dwarfdump: add support for .apple_types in --find
llvm-svn: 314479
2017-09-29 00:33:22 +00:00
Marek Sokolowski
ad66b459bd [llvm-rc] Add user-defined resources parsing ability. [8/8]
This allows llvm-rc to parse user-defined resources (ref:
msdn.microsoft.com/en-us/library/windows/desktop/aa381054.aspx).
These statements either import files, or put the specified raw data in
the resulting resource file.

Thanks to Nico Weber for his original work in this area.

Differential Revision: https://reviews.llvm.org/D37033

llvm-svn: 314478
2017-09-29 00:14:18 +00:00
Marek Sokolowski
469da485f8 [llvm-rc] Add integer expressions parsing ability. [7/8]
This allows the ints to be written as integer expressions evaluating to
unsigned 16-bit/32-bit integers.

All the expressions may use the following operators: + - & | ~, and
parentheses. Minus token - can be also unary. There is no precedence of
the operators other than the unary operators binding stronger than their
binary counterparts.

Differential Revision: https://reviews.llvm.org/D37022

llvm-svn: 314477
2017-09-28 23:53:25 +00:00
Jessica Paquette
74a7f13015 [MachineOutliner][NFC] Simplify logic in pruneCandidates
This commit yanks out the repeated sections of code in pruneCandidates into
two lambdas: ShouldSkipCandidate and Prune. This simplifies the logic in
pruneCandidates significantly, and reduces the chance of introducing bugs by
folding all of the shared logic into one place.

llvm-svn: 314475
2017-09-28 23:39:36 +00:00
Craig Topper
22309ec191 [X86] Don't select (cmp (and, imm), 0) to testw
Summary:
X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters.

I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs.

Reviewers: RKSimon, zvi, spatel

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38273

llvm-svn: 314474
2017-09-28 23:35:36 +00:00
Marek Sokolowski
c776b2e567 [llvm-rc] Fix-up for r314468 (argument-dependent lookup in make_unique).
llvm-svn: 314472
2017-09-28 23:12:53 +00:00
Matthias Braun
93c50f25a6 ARM: Fix cases where CSI Restored bit is not cleared
LR is an untypical callee saved register in that it is restored into a
different register (PC) and thus does not live-out of the return block.
This case requires the `Restored` flag in CalleeSavedInfo to be cleared.

This fixes a number of cases where this wasn't handled correctly yet.

llvm-svn: 314471
2017-09-28 23:12:06 +00:00
Yonghong Song
4e2902b1f7 bpf: fix a bug for disassembling ld_pseudo inst
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 314469
2017-09-28 22:47:34 +00:00
Marek Sokolowski
7414d53a94 [llvm-rc] Add VERSIONINFO parsing ability. [6/8]
This extends the set of llvm-rc parser's available resources by
another one, VERSIONINFO.

Ref: msdn.microsoft.com/en-us/library/windows/desktop/aa381058.aspx

Thanks to Nico Weber for his original work in this area.

Differential Revision: https://reviews.llvm.org/D37021

llvm-svn: 314468
2017-09-28 22:41:38 +00:00
Eugene Zelenko
dffcfd6adb [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 314467
2017-09-28 22:27:31 +00:00
Sanjay Patel
8eafe7cde0 [x86] add tests for possible insertelement to shuffle transform; NFC
See PR34716 and D38316 for more discussion.

llvm-svn: 314466
2017-09-28 22:27:25 +00:00
Ulrich Weigand
6e21950a9a [SystemZ] Fix fall-out from r314428
The expensive-checks build bot found a problem with the r314428 commit:
if CC is live after a ATOMIC_CMP_SWAPW instruction, it needs to be
marked as live-in to the block after the loop the pseudo gets expanded
to.  This actually fixes a code-gen bug as well, since if the CC isn't
live, the CR and JLH are merged to a CRJLH which doesn't actually set
the condition code any more.

llvm-svn: 314465
2017-09-28 22:08:25 +00:00
Craig Topper
48c31769eb [X86] Make use of vpmovwb when possible in LowerMULH
If we have BWI, we can truncate in a much simpler way by using vpmovwb. This even works without VLX by using the wider zmm->ymm truncate with a subvector extract.

Differential Revision: https://reviews.llvm.org/D38375

llvm-svn: 314457
2017-09-28 20:10:34 +00:00
Evgeniy Stepanov
c3bba818b4 Fix -Werror build.
/code/llvm-project/llvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp:260:38: error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture]
                                    [this](decltype(ObjLayer)::ObjHandleT,

llvm-svn: 314454
2017-09-28 19:43:53 +00:00
Martin Storsjo
54646a2723 [ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmp
In setupEntryBlockAndCallSites in CodeGen/SjLjEHPrepare.cpp,
we fetch and store the actual frame pointer, but on return via
the longjmp intrinsic, it always was restored into the r7 variable.

On windows, the frame pointer should be restored into r11 instead of r7.

On Darwin (where sjlj exception handling is used by default), the frame
pointer is always r7, both in arm and thumb mode, and likewise, on
windows, the frame pointer always is r11.

On linux however, if sjlj exception handling is enabled (which it isn't
by default), libcxxabi and the user code can be built in differing modes
using different registers as frame pointer. Therefore, when restoring
registers on a platform where we don't always use the same register
depending on code mode, restore both r7 and r11.

Differential Revision: https://reviews.llvm.org/D38253

llvm-svn: 314451
2017-09-28 19:04:30 +00:00
Martin Storsjo
ffe759d208 [ARM] Fix SJLJ exception handling when manually chosen on a platform where it isn't default
Differential Revision: https://reviews.llvm.org/D38252

llvm-svn: 314450
2017-09-28 19:04:14 +00:00
Matthias Braun
af31b5d762 MIR: Serialize CaleeSavedInfo Restored flag
llvm-svn: 314449
2017-09-28 18:52:14 +00:00
Craig Topper
b95348f94f [AVX512] Add avx512bw command lines to 128-bit idiv tests.
The multiply lowering on some of the tests can take advantage of the vpmovwb to simplify the truncate.

llvm-svn: 314448
2017-09-28 18:45:29 +00:00
Craig Topper
5f0415fda4 [X86] Use target independent ZERO_EXTEND/SIGN_EXTEND nodes were possible in LowerMULH
We aren't do any in register extends here so we should be able to just the target independent nodes directly and allow them to be lowered as necessary.

llvm-svn: 314447
2017-09-28 18:45:28 +00:00