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Author SHA1 Message Date
Daniel Dunbar
2b76a91c60 Trim trailing spaces (aka, trigger rebuild). 
llvm-svn: 96126
 2010-02-13 22:23:47 +00:00
Chris Lattner
d971210bd9 pull a bunch of huge inline methods in the PatternCodeEmitter 
class out of line.

llvm-svn: 96113
 2010-02-13 20:06:50 +00:00
Chris Lattner
b9c4a15ad5 teach the encoder to handle pseudo instructions like FP_REG_KILL, 
encoding them into nothing.

llvm-svn: 96110
 2010-02-13 19:16:53 +00:00
Chris Lattner
23368e55d7 remove dead code. 
llvm-svn: 96109
 2010-02-13 19:07:06 +00:00
Daniel Dunbar
e6679afaa7 MCAssembler: Fix pcrel relocations. Oh and, 
--
ddunbar@ozzy:tmp$ clang -m32 -integrated-as hello.c && ./a.out
hello world!
--

llvm-svn: 96096
 2010-02-13 09:45:59 +00:00
Daniel Dunbar
c05a38a3d3 MC/Mach-O: Start emitting fixups/relocations for instructions. 
llvm-svn: 96095
 2010-02-13 09:29:02 +00:00
Daniel Dunbar
7a1fd21459 MCAssembler: Switch MCAsmFixup to storing MCFixupKind instead of just a size. 
llvm-svn: 96094
 2010-02-13 09:28:54 +00:00
Daniel Dunbar
8e9044353a MCAssembler: Sink fixup list into MCDataFragment. 
llvm-svn: 96093
 2010-02-13 09:28:43 +00:00
Daniel Dunbar
95ae012b0e MCAssembler: Switch MCFillFragment to only taking constant values. Symbolic expressions can always be emitted as data + fixups. 
llvm-svn: 96092
 2010-02-13 09:28:32 +00:00
Daniel Dunbar
cc282ba52e MC/Mach-O: Implement EmitValue using data fragments + fixups instead of fill fragment. 
llvm-svn: 96091
 2010-02-13 09:28:22 +00:00
Daniel Dunbar
481e926468 MCAssembler: Start applying fixups in the data section. 
llvm-svn: 96090
 2010-02-13 09:28:15 +00:00
Daniel Dunbar
a699e834fb MCAssembler: Add assorted dump() methods. 
llvm-svn: 96089
 2010-02-13 09:28:03 +00:00
Daniel Dunbar
1581cae46f X86: Move extended MCFixupKinds into X86FixupKinds.h 
llvm-svn: 96088
 2010-02-13 09:27:52 +00:00
Chris Lattner
0874dc6dab Split some code out to a helper function (FindReusablePredBB) 
and add a doxygen comment.

Cache the phi entry to avoid doing tons of 
PHINode::getBasicBlockIndex calls in the common case.

On my insane testcase from re2c, this speeds up CGP from
617.4s to 7.9s (78x).

llvm-svn: 96083
 2010-02-13 05:35:08 +00:00
Chris Lattner
9c797fdf1d Speed up codegen prepare from 3.58s to 0.488s. 
llvm-svn: 96081
 2010-02-13 05:01:14 +00:00
Chris Lattner
975da20868 PHINode::getBasicBlockIndex is O(n) in the number of inputs 
to a PHI, avoid it in the common case where the BB occurs
in the same index for multiple phis.  This speeds up CGP on
an insane testcase from 8.35 to 3.58s.

llvm-svn: 96080
 2010-02-13 04:24:19 +00:00
Chris Lattner
1a067d53b0 iterate over preds using PHI information when available instead of 
using pred_begin/end.  It is much faster.

llvm-svn: 96079
 2010-02-13 04:15:26 +00:00
Chris Lattner
9be0b06335 speed up CGP a bit by scanning predecessors through phi operands 
instead of with pred_begin/end.

llvm-svn: 96078
 2010-02-13 04:04:42 +00:00
Chris Lattner
8530ba626c add encoder support and tests for rdtscp 
llvm-svn: 96076
 2010-02-13 03:42:24 +00:00
Johnny Chen
f252f7cf0d Add SETEND and BXJ instructions for disassembly only. 
llvm-svn: 96075
 2010-02-13 02:51:09 +00:00
Sean Callanan
0bc10793b0 Added the rdtscp instruction to the x86 instruction 
tables.

llvm-svn: 96073
 2010-02-13 02:06:11 +00:00
Jakob Stoklund Olesen
0a65533a38 Fix PR6283. 
When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072
 2010-02-13 02:06:10 +00:00
Dan Gohman
25722fd3fc Fix a pruning heuristic which implicitly assumed that SmallPtrSet is 
deterministically sorted.

llvm-svn: 96071
 2010-02-13 02:06:02 +00:00
Evan Cheng
6eb7ff5bbf Teach MachineFrameInfo to track maximum alignment while stack objects are being 
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069
 2010-02-13 01:56:41 +00:00
Jakob Stoklund Olesen
8ce1b3d280 Enable the inlinehint attribute in the Inliner. 
Functions explicitly marked inline will get an inlining threshold slightly
more aggressive than the default for -O3. This means than -O3 builds are
mostly unaffected while -Os builds will be a bit bigger and faster.

The difference depends entirely on how many 'inline's are sprinkled on the
source.

In the CINT2006 suite, only these tests are significantly affected under -Os:

               Size   Time
471.omnetpp   +1.63% -1.85%
473.astar     +4.01% -6.02%
483.xalancbmk +4.60%  0.00%

Note that 483.xalancbmk runs too quickly to give useful timing results.

llvm-svn: 96066
 2010-02-13 01:51:53 +00:00
Sean Callanan
9806eade6e Fixed encodings for invlpg, invept, and invvpid. 
llvm-svn: 96065
 2010-02-13 01:48:34 +00:00
Daniel Dunbar
09733841aa MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'. 
llvm-svn: 96064
 2010-02-13 01:28:07 +00:00
Johnny Chen
727c71d8ac Added a bunch of saturating add/subtract instructions for disassembly only. 
llvm-svn: 96063
 2010-02-13 01:21:01 +00:00
Chris Lattner
d4fe983f23 rip out the 'heinous' x86 MCCodeEmitter implementation. 
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059
 2010-02-13 00:49:29 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Bob Wilson
5d66f81412 Besides removing phi cycles that reduce to a single value, also remove dead 
phi cycles.  Adjust a few tests to keep dead instructions from being optimized
away.  This (together with my previous change for phi cycles) fixes Apple
radar 7627077.

llvm-svn: 96057
 2010-02-13 00:31:44 +00:00
Dan Gohman
1e93b1c022 Override dominates and properlyDominates for SCEVAddRecExpr, as a 
SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated
by all of its operands. This fixes an abort compiling 403.gcc.

llvm-svn: 96056
 2010-02-13 00:19:39 +00:00
Daniel Dunbar
4ef0be5df5 MC/X86: Push immediate operands as immediates not expressions when possible. 
llvm-svn: 96055
 2010-02-13 00:17:21 +00:00
Jeffrey Yasskin
963eee9ee1 Make PassRegistrar thread-safe since it can be modified by code running in 
separate LLVMContexts.

llvm-svn: 96051
 2010-02-13 00:03:17 +00:00
Chris Lattner
1d25e3978d Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Chris Lattner
c80a6de0a9 add some disassemble testcases for weird instructions 
llvm-svn: 96045
 2010-02-12 23:46:48 +00:00
Sean Callanan
21a160f4bf Reworked the Intel disassembler to support instructions 
whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043
 2010-02-12 23:39:46 +00:00
Chris Lattner
4170bb81da implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00
Dale Johannesen
08f0ab42b8 Add the problem I just hacked around in 96015/96020. 
The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039
 2010-02-12 23:16:24 +00:00
Chris Lattner
946403d05f give MCCodeEmitters access to the current MCContext. 
llvm-svn: 96038
 2010-02-12 23:12:47 +00:00
Jeffrey Yasskin
72e77cf286 Make JIT::runFunction clean up the generated stub function. 
Patch by Shivram K!

llvm-svn: 96037
 2010-02-12 23:05:31 +00:00
Chris Lattner
e90d092fd7 implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036
 2010-02-12 23:00:36 +00:00
Johnny Chen
d36727232c Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032
 2010-02-12 22:53:19 +00:00
Chris Lattner
0a7654c7c9 pull the rip-relative addressing mode case up early. 
llvm-svn: 96031
 2010-02-12 22:47:55 +00:00
Chris Lattner
3df1321651 fixme resolved! 
llvm-svn: 96029
 2010-02-12 22:39:06 +00:00
Chris Lattner
1e01ac75bc start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
llvm-svn: 96028
 2010-02-12 22:36:47 +00:00
Bob Wilson
881d06c0b9 Fix a comment typo. 
llvm-svn: 96027
 2010-02-12 22:34:54 +00:00
Chris Lattner
f1f926247f enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026
 2010-02-12 22:27:07 +00:00
Evan Cheng
c2084b74bb Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
llvm-svn: 96023
 2010-02-12 22:17:21 +00:00
Dale Johannesen
d52ea2ffc6 This should have gone in with 26015, see comments there. 
llvm-svn: 96020
 2010-02-12 22:00:40 +00:00