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Commit Graph

15 Commits

Author SHA1 Message Date
Stephen Lin
3ae734a60c Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.

llvm-svn: 186258
2013-07-13 20:38:47 +00:00
Jakob Stoklund Olesen
b38d4fe021 Remove some register allocation order dependencies.
llvm-svn: 172874
2013-01-19 00:03:32 +00:00
Bob Wilson
ee6a40c517 Add LLVM support for Swift.
llvm-svn: 164899
2012-09-29 21:43:49 +00:00
Bob Wilson
886994b683 Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default.  We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

llvm-svn: 129772
2011-04-19 18:11:45 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
2010-10-28 01:49:06 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
llvm-svn: 104307
2010-05-21 00:43:17 +00:00
Jim Grosbach
2a0b14a387 switch the flag for using NEON for SP floating point to a subtarget 'feature'.
Re-commit. This time complete with testsuite updates.

llvm-svn: 99570
2010-03-25 23:47:34 +00:00
Edward O'Callaghan
d1c7b40bb5 Convert ARM tests to FileCheck for PR5307.
llvm-svn: 89593
2009-11-22 14:23:33 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
David Goodwin
a4b73e486e Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
llvm-svn: 83218
2009-10-01 22:19:57 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
David Goodwin
c0fe95d8ce Make NEON single-precision FP support the default for cortex-a8 (again).
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
llvm-svn: 78081
2009-08-04 17:53:06 +00:00