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2d819b93a2
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1998 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
2d819b93a2 Remove the JustSP single-register regclass. 
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280
 2010-01-13 00:43:06 +00:00
Johnny Chen
f782ccee01 Minor change, change the order of two "let Inst{...}" stmts within multiclass 
T2I_bin_ii12rs definition.

llvm-svn: 93006
 2010-01-08 17:41:33 +00:00
Jim Grosbach
40aafaec86 80 column violations 
llvm-svn: 92876
 2010-01-06 23:54:42 +00:00
Jakob Stoklund Olesen
a63aa4e54b Add Target hook to duplicate machine instructions. 
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

llvm-svn: 92873
 2010-01-06 23:47:07 +00:00
Jim Grosbach
76768e7216 Addressing mode 6 (load/store) instructions can't encode an immediate offset 
for stack references.

llvm-svn: 92871
 2010-01-06 23:45:18 +00:00
Johnny Chen
6ae7666885 Undo r92785, it caused test failure. 
llvm-svn: 92796
 2010-01-05 22:37:28 +00:00
Johnny Chen
f15fb27ffd Add Rt2 to the asm format string for 32-bit Thumb load/store register dual 
instructions.  Thumb does not have the restriction that t2 = t+1.

llvm-svn: 92785
 2010-01-05 21:51:46 +00:00
Dan Gohman
9bcfdf98f1 Change SelectCode's argument from SDValue to SDNode *, to make it more 
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
 2010-01-05 01:24:18 +00:00
Benjamin Kramer
798349c4d1 Add missing include (for inline PATypeHolder::get). 
llvm-svn: 92222
 2009-12-28 12:27:56 +00:00
Bill Wendling
4e43e78b2e Remove dead variable. 
llvm-svn: 92193
 2009-12-28 01:57:39 +00:00
Bill Wendling
baec6e54f4 Add an "ATTRIBUTE_UNUSED" macro (and use it). It's for variables which are 
mainly used in debugging and/or assert situations. It should make the compiler
and the static analyzer stop nagging us about them.

llvm-svn: 92181
 2009-12-28 01:20:29 +00:00
Jakob Stoklund Olesen
e82ce92826 Move kill flags when the same register occurs more than once in a sequence. 
llvm-svn: 92058
 2009-12-23 21:34:03 +00:00
Jakob Stoklund Olesen
17a89f1f8a Handle undef operands properly. 
llvm-svn: 92054
 2009-12-23 21:28:42 +00:00
Jakob Stoklund Olesen
f18e89a0bf Make insert position available to MergeOpsUpdate. 
Rearrange arguments.
No functional changes

llvm-svn: 92053
 2009-12-23 21:28:37 +00:00
Jakob Stoklund Olesen
55c03c7cef Perform kill flag calculations in new method. No functional changes. 
llvm-svn: 92052
 2009-12-23 21:28:31 +00:00
Jakob Stoklund Olesen
423f1e70e6 Move repeated code to a new method. No functional change. 
llvm-svn: 92051
 2009-12-23 21:28:23 +00:00
Jakob Stoklund Olesen
9d1c8ecf05 Add a SPR register class to the ARM target. 
Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944
 2009-12-22 23:54:44 +00:00
Jakob Stoklund Olesen
affe25dbaf Use proper move instructions. Make the verifier happy. 
llvm-svn: 91914
 2009-12-22 18:49:55 +00:00
Bill Wendling
fc4c238bd5 Add more plumbing. This time in the LowerArguments and "get" functions which 
return partial registers. This affected the back-end lowering code some.

Also patch up some places I missed before in the "get" functions.

llvm-svn: 91880
 2009-12-22 02:10:19 +00:00
Evan Cheng
c46a0ba3fc Delete the instruction just before the function terminates for consistency sake. 
llvm-svn: 91836
 2009-12-21 19:53:39 +00:00
Douglas Gregor
f39dd74a3f Fix a bunch of little errors that Clang complains about when its being pedantic 
llvm-svn: 91764
 2009-12-19 07:05:23 +00:00
Rafael Espindola
4f903d4548 Fix libstdc++ build on ARM linux and part of PR5770. 
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.

Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.

For a patch that make us detect problems like this earlier, take a look at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html

With that patch we assert as soon and the new instruction is added to the garbage set.

llvm-svn: 91691
 2009-12-18 16:59:39 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
Johnny Chen
04b3259f9d Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
John McCall
8ee507f0f5 Silence a clang warning about the deprecated (but perfectly reasonable in 
context) increment-of-bool idiom.

llvm-svn: 91564
 2009-12-16 20:31:50 +00:00
Jim Grosbach
666c19db99 Mark STREX* as earlyclobber for the success result register. 
llvm-svn: 91555
 2009-12-16 19:44:06 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
John McCall
e3df19422d Every anonymous namespace is different. Caught by clang++. 
llvm-svn: 91481
 2009-12-16 00:15:28 +00:00
Jeffrey Yasskin
d50951dc1e Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464
 2009-12-15 22:42:46 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Jim Grosbach
76d722dd6c nand atomic requires opposite operand ordering 
llvm-svn: 91371
 2009-12-15 00:12:35 +00:00
Johnny Chen
61b6d221d2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

llvm-svn: 91339
 2009-12-14 21:51:34 +00:00
Jim Grosbach
dc0006c895 v6 sync insn copy/paste error 
llvm-svn: 91333
 2009-12-14 21:33:32 +00:00
Jim Grosbach
09167e5bbb Add ARMv6 memory and sync barrier instructions 
llvm-svn: 91329
 2009-12-14 21:24:16 +00:00
Johnny Chen
80b7b55eea Fixed encoding bits typo of ldrexd/strexd. 
llvm-svn: 91327
 2009-12-14 21:01:46 +00:00
Jim Grosbach
266c2d59e6 Thumb2 atomic operations 
llvm-svn: 91321
 2009-12-14 20:14:59 +00:00
Jim Grosbach
c7285dc721 correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
llvm-svn: 91313
 2009-12-14 19:24:11 +00:00
Jim Grosbach
723a7aa4e9 add Thumb2 atomic and memory barrier instruction definitions 
llvm-svn: 91310
 2009-12-14 18:56:47 +00:00
Jim Grosbach
99ace7c9ff whitespace 
llvm-svn: 91307
 2009-12-14 18:36:32 +00:00
Jim Grosbach
aaf39891f4 ARM memory barrier instructions are not predicable 
llvm-svn: 91305
 2009-12-14 18:31:20 +00:00
Jim Grosbach
5741d33c74 add ldrexd/strexd instructions 
llvm-svn: 91284
 2009-12-14 17:02:55 +00:00
Jim Grosbach
87975f6229 atomic binary operations up to 32-bits wide. 
llvm-svn: 91260
 2009-12-14 04:22:04 +00:00
Jim Grosbach
187ad02a4f Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200
 2009-12-12 01:40:06 +00:00
Jim Grosbach
0cfc544e97 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around. 
llvm-svn: 91150
 2009-12-11 20:29:53 +00:00
Johnny Chen
5d6f117ed5 Store Register Exclusive should leave the source register Inst{3-0} unspecified. 
llvm-svn: 91143
 2009-12-11 19:37:26 +00:00
Jim Grosbach
89e51fb5ff Update properties. 
llvm-svn: 91140
 2009-12-11 18:52:41 +00:00
Jim Grosbach
5a1c16e5bb Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. 
llvm-svn: 91090
 2009-12-11 01:42:04 +00:00
Jim Grosbach
608ef114aa Add instruction encoding for DMB/DSB 
llvm-svn: 91053
 2009-12-10 18:35:32 +00:00
Jim Grosbach
be89da9845 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. 
llvm-svn: 91003
 2009-12-10 00:11:09 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00