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Author SHA1 Message Date
Dan Gohman
0f859353ea Revert r67655 and r67656, as they are breaking the build. I'm 
not going to persue this further at this time.

llvm-svn: 67666
 2009-03-25 00:52:11 +00:00
Chris Lattner
c055403764 Fix PR3874 by restoring a condition I removed, but making it more 
precise than it used to be.

llvm-svn: 67662
 2009-03-25 00:28:58 +00:00
Devang Patel
225831fc9e Do not ignore DW_TAG_class_type! 
llvm-svn: 67661
 2009-03-25 00:28:40 +00:00
Dan Gohman
ec41ca9857 LLVM's master Makefile.common is in LLVM_SRC_ROOT, not LLVM_OBJ_ROOT. 
llvm-svn: 67658
 2009-03-25 00:09:05 +00:00
Chris Lattner
be6ee56fb2 oops, I intended to remove this, not comment it out. Thanks Duncan! 
llvm-svn: 67657
 2009-03-24 23:48:25 +00:00
Dan Gohman
22ad86c5be Regenerate configure. 
llvm-svn: 67656
 2009-03-24 23:47:11 +00:00
Dan Gohman
2175f600ab Fix paths; AutoRegen.sh changes its current working directory to be the 
autoconf directory, but these paths need to be relative to the main
source directory.

llvm-svn: 67655
 2009-03-24 23:46:25 +00:00
Dan Gohman
91dd40133b Update for autoconf 2.6x; 
llvm-svn: 67654
 2009-03-24 23:45:13 +00:00
Misha Brukman
6e86395ae7 Converted a1.ll to unittests. 
llvm-svn: 67652
 2009-03-24 21:36:09 +00:00
Duncan Sands
dd613ae0dd Mention explicitly that the Ada front-end will not bootstrap. 
The configure line had --disable-bootstrap, but it was not
clear that this is essential.

llvm-svn: 67651
 2009-03-24 21:16:39 +00:00
Evan Cheng
758c95f07a Fix PR3845: Avoid stale MachineInstruction pointer reference. 
llvm-svn: 67649
 2009-03-24 20:33:17 +00:00
Dan Gohman
81d906ee93 Fix bash-isms. 
llvm-svn: 67647
 2009-03-24 20:21:37 +00:00
Gabor Greif
c988c96b3e simplify logic and get rid of the assumption that operand 0 is the callee 
llvm-svn: 67642
 2009-03-24 19:28:39 +00:00
Chris Lattner
aabd3eeeff canonicalize inttoptr and ptrtoint instructions which cast pointers 
to/from integer types that are not intptr_t to convert to intptr_t
then do an integer conversion to the dest type.  This exposes the
cast to the optimizer.

llvm-svn: 67638
 2009-03-24 18:35:40 +00:00
Dale Johannesen
17dddcd886 fix one more fp80 case (used only by Interpreter) 
and streamline code here a bit.

llvm-svn: 67636
 2009-03-24 18:16:17 +00:00
Chris Lattner
51a4134e1c two changes: 
1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1).  This 
   exposes the AND to other instcombine xforms and is more of what the code
   generator expects.
2. Rewrite the remaining trunc pattern match to use 'match', which 
   simplifies it a lot.
   

llvm-svn: 67635
 2009-03-24 18:15:30 +00:00
Dale Johannesen
68e30cdf59 Change JIT for different layout of fp80. 
llvm-svn: 67629
 2009-03-24 17:35:45 +00:00
Dan Gohman
edd5fa3721 Add a testcase for the scheduling heuristic introduced in r67586. 
llvm-svn: 67622
 2009-03-24 16:38:27 +00:00
Chris Lattner
135eeefe66 more tidying: name the components of PhysReg in the case when 
the target constraint specifies a specific physreg.

llvm-svn: 67618
 2009-03-24 15:27:37 +00:00
Chris Lattner
8793e812ef Tidy a bit more. 
llvm-svn: 67617
 2009-03-24 15:25:07 +00:00
Chris Lattner
a60dd19c3e simplify this code a bit now that "allocation to a vreg class" can never 
fail.

llvm-svn: 67616
 2009-03-24 15:22:11 +00:00
Dan Gohman
7a9e8cbf79 I was convinced that it's ok to allow a second i8 return value 
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.

llvm-svn: 67588
 2009-03-24 01:04:34 +00:00
Dan Gohman
547cfc882e Minor compile-time optimization; don't bother checking 
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

llvm-svn: 67587
 2009-03-24 00:50:07 +00:00
Dan Gohman
e6d7478bc1 Add a pre-pass to the burr-list scheduler which makes adjustments to 
help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.

llvm-svn: 67586
 2009-03-24 00:49:12 +00:00
Evan Cheng
b3196f1298 Do not emit comments unless -asm-verbose. 
llvm-svn: 67580
 2009-03-24 00:17:40 +00:00
Dale Johannesen
0f8e2bcd98 Use a SmallPtrSet instead of std::set. 
llvm-svn: 67578
 2009-03-23 23:39:20 +00:00
Evan Cheng
702a8b4399 Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. 
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574
 2009-03-23 22:57:19 +00:00
Ted Kremenek
261cd6c4c3 Add sanity check in Clang TableGen backend to check if 'Component' is a string. 
llvm-svn: 67565
 2009-03-23 21:54:33 +00:00
Dale Johannesen
34123aba43 Fix internal representation of fp80 to be the 
same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562
 2009-03-23 21:16:53 +00:00
John Mosby
6813f07224 README.txt: test commit w/blank line appended 
llvm-svn: 67560
 2009-03-23 21:00:45 +00:00
Dan Gohman
60c652de57 When unfolding a load during scheduling, the new operator node has 
a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.

And add a few comments.

llvm-svn: 67554
 2009-03-23 20:20:43 +00:00
Evan Cheng
e09988f66b Update test for pr3864. 
llvm-svn: 67545
 2009-03-23 18:27:36 +00:00
Evan Cheng
7e4a6972d6 Fix PR3391 and PR3864. Reg allocator infinite looping. 
llvm-svn: 67544
 2009-03-23 18:24:37 +00:00
Dan Gohman
a6842708e6 Don't set SUnit::hasPhysRegDefs to true unless the defs are 
actually have uses, which reflects the way it's used.

llvm-svn: 67540
 2009-03-23 17:39:36 +00:00
Dan Gohman
b6b24c5fc1 Fix canClobberPhysRegDefs to check all SDNodes grouped together 
in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.

llvm-svn: 67531
 2009-03-23 16:23:01 +00:00
Dan Gohman
78a1698ac0 Add a new bit to SUnit to record whether a node has implicit physreg 
defs, regardless of whether they are actually used.

llvm-svn: 67528
 2009-03-23 16:10:52 +00:00
Dan Gohman
18daca0895 Now that errs() is properly non-buffered, there's no need to 
explicitly flush it.

llvm-svn: 67526
 2009-03-23 15:57:19 +00:00
Dan Gohman
b3e085e222 Clarify a comment. 
llvm-svn: 67525
 2009-03-23 15:54:02 +00:00
Dan Gohman
b10c534b89 LoopVR is not CFGOnly. 
llvm-svn: 67524
 2009-03-23 15:50:52 +00:00
Dan Gohman
9ef382068e Enhance LiveValues to work on PHI operands. 
llvm-svn: 67523
 2009-03-23 15:49:37 +00:00
Dan Gohman
5be4b3a1f4 Make getOperandNumForIncomingValue and getOperandNumForIncomingBlock 
static member functions, and add getIncomingValueNumForOperand
and getIncomingBlockNumForOperand, which are the respective
inverses.

llvm-svn: 67522
 2009-03-23 15:48:29 +00:00
Dan Gohman
e9cf3083d2 Correct some comments. Operand numbers start at 0. 
llvm-svn: 67518
 2009-03-23 15:40:10 +00:00
Evan Cheng
2ec94dd447 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 
llvm-svn: 67512
 2009-03-23 08:01:15 +00:00
Evan Cheng
4b11d96b62 Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.

llvm-svn: 67511
 2009-03-23 07:19:58 +00:00
Chris Lattner
095a3938e4 fix a bug Alexei Svitkine pointed out. 
llvm-svn: 67510
 2009-03-23 06:46:20 +00:00
Chris Lattner
910f31715e When we restore signal handlers, restore them back to what they 
were when we came around, not to their default handler.  This 
should fix PR3848

llvm-svn: 67509
 2009-03-23 05:55:36 +00:00
Chris Lattner
429a82ad30 factorize signal registration, part of PR3848. 
llvm-svn: 67508
 2009-03-23 05:42:29 +00:00
Dan Gohman
745c0acc79 Fix a grammaro in a comment that Bill noticed. 
llvm-svn: 67507
 2009-03-23 05:02:44 +00:00
Chris Lattner
5e7dd59063 tt'ify. 
llvm-svn: 67505
 2009-03-23 04:53:34 +00:00
Chris Lattner
750312aa5e VC++ 6.0 is not future work :) 
Do not recommend llvm::OStream anymore.  Use raw_ostream or MemoryBuffer.

llvm-svn: 67504
 2009-03-23 04:52:53 +00:00