Evan Cheng
9f0ffdf4b3
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Chris Lattner
844e3a4191
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
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llvm-svn: 36660
2007-05-03 00:32:00 +00:00
Evan Cheng
8d374caead
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng
7cbde8351a
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
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llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng
fe7242e9bb
Get rid of references to iostream.
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llvm-svn: 34009
2007-02-07 21:18:32 +00:00
Evan Cheng
b3ff5f65d4
Select add FI, c correctly.
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llvm-svn: 33960
2007-02-06 09:11:20 +00:00
Evan Cheng
c4ba711e91
- Store val, [sp, c] must be selected to tSTRsp.
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- If c does not fit in the offset field, materialize sp + c into a register
using tADDhirr.
llvm-svn: 33944
2007-02-06 00:22:06 +00:00
Evan Cheng
99a2f7d598
Change the operand orders to t_addrmode_s* to make it easier to morph
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instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
Evan Cheng
c6db78ab84
Use PC relative ldr to load from a constantpool in Thumb mode.
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llvm-svn: 33484
2007-01-24 08:53:17 +00:00
Evan Cheng
1630c86beb
Allow [ fi#c, imm ] as ARM load / store addresses.
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llvm-svn: 33474
2007-01-24 02:45:25 +00:00
Evan Cheng
fa613cdd06
Various Thumb mode load / store isel bug fixes.
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llvm-svn: 33472
2007-01-24 02:21:22 +00:00
Evan Cheng
5f947e4e2f
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
...
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
Evan Cheng
c6e1d453d3
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio
97e120a71c
Build constants using instructions mov/orr or mvn/eor.
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llvm-svn: 33141
2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio
078b85bdaa
Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
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llvm-svn: 32870
2007-01-04 14:01:38 +00:00
Rafael Espindola
d1baea3471
implement missing compares
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patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
Reid Spencer
dda168599d
For PR950:
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Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
Rafael Espindola
16af307d42
fix comment
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llvm-svn: 32767
2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio
7bfe536783
Implement SELECT_CC (f32/f64) for ARM.
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llvm-svn: 32762
2006-12-28 13:11:14 +00:00
Rafael Espindola
d19ea53887
avoid using a constant table when a constant can be used inline
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llvm-svn: 32580
2006-12-14 18:58:37 +00:00
Rafael Espindola
7c4245c4e3
more general matching of the MVN instruction
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llvm-svn: 32484
2006-12-12 17:10:13 +00:00
Rafael Espindola
a65fd68f23
don't use "ordinary" addressing mode 1 when mvn is appropriate
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llvm-svn: 32482
2006-12-12 14:03:29 +00:00
Rafael Espindola
d29cb12dfc
use MVN to handle small negative constants
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llvm-svn: 32459
2006-12-12 01:03:11 +00:00
Bill Wendling
f13d78d3b8
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Rafael Espindola
5e8a6ca4c0
expand memmove and memcpy
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llvm-svn: 32226
2006-12-05 17:57:23 +00:00
Rafael Espindola
38062acebb
add support for the "r" asm constraint
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patch by Lauro Ramos Venancio
llvm-svn: 32224
2006-12-05 17:37:31 +00:00
Rafael Espindola
5daebfdae0
implement load effective address similar to the alpha backend
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remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
Evan Cheng
736a8eb3cd
Match tblegen changes.
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llvm-svn: 31571
2006-11-08 20:34:28 +00:00
Rafael Espindola
f7b898d497
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Rafael Espindola
04afe6eb37
move ARMCondCodeToString to ARMAsmPrinter.cpp
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remove unused variables from lowerCall
llvm-svn: 31378
2006-11-02 15:00:02 +00:00
Evan Cheng
5766dd6455
All targets expand BR_JT for now.
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llvm-svn: 31294
2006-10-30 08:02:39 +00:00
Rafael Espindola
99322ef58c
initial support for frame pointers
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llvm-svn: 31197
2006-10-26 13:31:26 +00:00
Rafael Espindola
a962656c07
expand ISD::VACOPY
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llvm-svn: 31170
2006-10-24 20:15:21 +00:00
Rafael Espindola
357f151d9d
expand ISD::MEMSET
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llvm-svn: 31137
2006-10-23 20:08:22 +00:00
Reid Spencer
d414793dbc
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
Rafael Espindola
17544c1c1d
expand SIGN_EXTEND_INREG
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llvm-svn: 31046
2006-10-19 12:06:50 +00:00
Rafael Espindola
6cc20c7950
expand brind so that we don't have to implement jump tables right now
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llvm-svn: 31045
2006-10-19 10:56:43 +00:00
Rafael Espindola
80c7461ada
implement CallingConv::Fast as CallingConv::C
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llvm-svn: 31034
2006-10-18 12:03:07 +00:00
Rafael Espindola
58233f9db2
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
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llvm-svn: 31014
2006-10-17 21:05:33 +00:00
Rafael Espindola
47970f96ac
initial implementation of addressing mode 5
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llvm-svn: 31002
2006-10-17 18:04:53 +00:00
Rafael Espindola
4f61431679
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
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llvm-svn: 30987
2006-10-16 21:10:32 +00:00
Rafael Espindola
c426cede28
expand ISD::BRCOND
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llvm-svn: 30963
2006-10-14 17:59:54 +00:00
Rafael Espindola
38c602f658
fix some fp condition codes
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use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
Evan Cheng
fe5bb5dbe6
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
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llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Rafael Espindola
24d7976d1d
implement calls to functions that return long
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llvm-svn: 30929
2006-10-13 16:47:22 +00:00
Rafael Espindola
bd50a4d757
implement unordered floating point compares
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llvm-svn: 30928
2006-10-13 13:14:59 +00:00
Rafael Espindola
46e7aceb1d
uint <-> double conversion
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llvm-svn: 30862
2006-10-10 20:38:57 +00:00
Rafael Espindola
27d68a3c22
add double <-> int conversion
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llvm-svn: 30858
2006-10-10 18:55:14 +00:00
Rafael Espindola
413aa20bc8
compare doubles
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llvm-svn: 30856
2006-10-10 16:33:47 +00:00